Re: Stopping the clock for power management

Ndf wrote:

> Hello,
>
> For a low power application I would like to stop the clock feed into a FPGA
> when enter “sleep mode”. This is a common practice or can be dangerous? And
> if is dangerous why? Maybe a silly question but I want to be sure about
> that! I use Lattice XP parts.


You can stop the clock, and also reduce Vcc in some cases.

However, Static Icc on these new FPGAs can be a real killer!

Look at some of the new Power control Busses / Chips appearing, that are
designed to ramp the Vcc, as the clock scales.
Natsemi LP5550 is one example.
-jg

.

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