Re: How to evaluate the space efficiency of a historic design.

On 29 Jun 2006 12:42:18 -0700, "Paul Marciano" <pm940@xxxxxxxxx>
wrote:

Before I start let me say I'm not sure this is either an intelligent
question nor an answerable one... so please be gentle.

I'm looking at implementing an 8-bit processor clone on an FPGA (purely
academic exercise - I know there are free IP cores available) and am
wondering how to judge the space efficiency of my design (as opposed to
speed efficiency).

According to numbers found on the web the MOS 6502 has 9000
transistors.

I haven't written a single line of RTL yet, but say I implemented a
100% functional equivalent in a 200K gate Spartan3, and it uses up 25%
of the resources... How would you judge that?

Would you just take your own experience and say, "That's 3x too big...
try again".

Would knowing it can be done in 9000 custom placed transistors help at
all in judging the relative efficiency of the FPGA implementation?


Regards,
Paul.

Let me do a rough calculation here:
9000 transistors assuming 6502 had no memory can be used to generate
2250 2 input NAND gates. S3200 has 4320 logic cells (1 flop + 1 lookup
table); assuming a 4 input look up table is around 3 nand2 and a flop
is around 5 nand2, I'd say it has 34560 equivalent nand2s so 25% would
be 8640 gates and that would be around 4x too big; again very roughly
and I am sure lots of people would disagree but I think it's a
reasonable starting point.
.

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