Re: NCO Clock driven Designs in FPGA
- From: Ray Andraka <ray@xxxxxxxxxxx>
- Date: Thu, 29 Jun 2006 14:23:26 -0400
rajeev wrote:
Hi everyone,
I have a few doubts that are not being addressed in fpga groups(at
least i could not find the one ) though it is very common in DSP design
using FPGAs.
1. In many a communication receiver systems a resampler (NCO based) is
required. The output of the resampler is fed to other logics. Can NCO
output be used to drive the portion of the design ? as is sayed that in
FPGA clock derived from (combinational/sequential) logics should be
avoided and whenever a rate change is required use enable signal
instead. But this approach requires the whole design to be run at the
highest clock consuming much more power.What could be the power
efficent method of doing the same.
Most common example is a CIC filter used for large rate change (Not by
integer factor but rather rate change is driven by a NCO) where input
is at much higher rate while the output is at lower rate.
2. If at all NCO is used for clocking the design that is required to
run at much slower speed what care should be the taken for NCO master
clock driving NCO , to NCO output clock ? (I feel higher the ratio
lower the jitter will be).
3. Can NCO clock be further used to drive a DCM to produce a high freq
clock that can be used for serial MAC fir (for efficient fpga fabric
usage.)
regards.
rajeev shukla.
The NCO isn't a sample rate changer, it, along with a mixer will move your signal to base-band where you can then low pass filter it and decimate it to reduce the sample rate to something in line with the bandwidth of your signal after filtering. For large rate changes, a CIC filter does make sense. You'll still need additional filters in most cases to improve the Q of the resulting filter bank. Typically, I use a CIC filter followed by two stages of decimate by 2 FIR filters.
Rather than changing the clock rate, it is far easier to use clock enables to flag when good data is present at the decimated rate. This is especially true when you don't know what the output sample rate is going to be because of a programmable bandwidth and decimation ratio.
Your downstream design can take advantage of the fact that for a given output sample rate there are N invalid samples between each valid sample. Use those spare clock cycles to reduce the size of the hardware with a combination of bit- or digit-serial computation and sequential computation (in other words trade the spare clock cycles for smaller hardware). Your limitation is the minimum number of clocks per sample, which occurs with the highest output sample rate that you can set the design up for. Many wireless designs have a fairly high minimum decimation ratio, so everything after the CIC filter can be bit serial and might even be shared between multiple channels if the bnadwidth of all the channels is the same. The comb side of the CIC filter can also be made bit serial to save some additional hardware.
If there is a fixed integer division in the sample rate, then you can use a divided clock if that makes sense for your design. You should probably avoid an arbitrary non-integer clock divide because getting the data reliably across the clock domain and servo-ing the clock so that you don't have data over or underruns is a rather hard design to get right. If you do need that, then you probably need to be looking at more sophisticated resampling such as a Farrow resampler.
.
- References:
- NCO Clock driven Designs in FPGA
- From: rajeev
- NCO Clock driven Designs in FPGA
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