Re: NCO Clock driven Designs in FPGA

"rajeev" <shuklrajeev@xxxxxxxxx> wrote in message
news:1151562326.692337.229940@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
Hi everyone,
I have a few doubts that are not being addressed in fpga groups(at
least i could not find the one ) though it is very common in DSP design
using FPGAs.

1. In many a communication receiver systems a resampler (NCO based) is
required. The output of the resampler is fed to other logics. Can NCO
output be used to drive the portion of the design ? as is sayed that in
FPGA clock derived from (combinational/sequential) logics should be
avoided and whenever a rate change is required use enable signal
instead. But this approach requires the whole design to be run at the
highest clock consuming much more power.What could be the power
efficent method of doing the same.
Most common example is a CIC filter used for large rate change (Not by
integer factor but rather rate change is driven by a NCO) where input
is at much higher rate while the output is at lower rate.

2. If at all NCO is used for clocking the design that is required to
run at much slower speed what care should be the taken for NCO master
clock driving NCO , to NCO output clock ? (I feel higher the ratio
lower the jitter will be).

3. Can NCO clock be further used to drive a DCM to produce a high freq
clock that can be used for serial MAC fir (for efficient fpga fabric
usage.)

regards.
rajeev shukla.


"DCM" suggests Xilinx, so...

The NCO output can be fed to a BUFGMUX to drive other logic, no problem.
The reason the clock enables are suggested in many designs is to keep the
clock domains between the full speed and lower speed portions of the circuit
in the same clock domain, eliminating problems with crossing imprecisely
aligned clocks. If you need to communicate between the NCO (or other logic
driven by the master clock) and logic driven by the NCO's clock, you need to
worry about crossing time domains.

Higher clocks for the NCO (or DDS) produce less jitter, certainly. Often
jitter at this level doesn't matter in circuits; only when crossing to or
from the analog realm (such as an ethernet PHY) is jitter critical.

The DCM should have troubles if fed a clock with high jitter. There are
specific jitter specs included for the DCM input in the DC & Switching
Characteristics for your device. It's tough to establish a lock in a delay
line based architecture when the clock is always way too early or way too
late. If you need a "clean" clock, consider an A/D to generate a true DDS
sinewave or, better yet, use a clock chip such as the IDT5V9885 to clean up
the NCO-generated jitter. You can get a more expensive zero-delay buffer
style of jitter cleanup with an ICS part.


.

Relevant Pages

  • NCO Clock driven Designs in FPGA
    ... In many a communication receiver systems a resampler (NCO based) is ... FPGA clock derived from logics should be ... Most common example is a CIC filter used for large rate change (Not by ...
    (comp.arch.fpga)
  • Re: 64 bit division compensate NCO
    ... get a new delta phase value for the NCO sounds more like a LOW fidelity ... your clocks are in the range of 1 GHz (and that your fpga can handle clocks ... decreasing clock frequencies. ...
    (comp.arch.fpga)
  • Re: what is the correct way to capture ADC using fpga
    ... use the clean clock that feeds the ADC to run the FPGA. ... The jitter is the problem. ...
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  • Re: 64 bit division compensate NCO
    ... clock uses 10MHz and I've purposely change its timebase to 1.6ms. ... delta phase accordantly. ... I can't use the external clock reference because the nco ... you do, you don't need the frequency measurement from somewhere else, ...
    (comp.arch.fpga)
  • Re: 64 bit division compensate NCO
    ... I can't use the external clock reference because the nco ... 125MHz clock to drive it,, only with hardware changes can I change ... If you do, you don't need the frequency measurement from somewhere else, you use the clocks themselves and the counter arrangement I described. ... A more conventional approach would be to not worry about the specific delta, but instead nudge it up or down with feedback derived from the frequency or phase error at the NCO output. ...
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