Re: Generic synthesis target in Synplify Pro

Only one restriction comes to mind:

DDR logic (two clocks or both edges of one clock) will only synthesize
to targets that have DDR resources (usually IO registers).

Arrays will (with the appropriate restrictions) synthesize to ram on
devices that support it, or to registers on targets that don't, but
they will always synthesize, regardless of the target.

Andy


Ben Jones wrote:

Generally, if code is synthesizable for one chip it is synthesizable for
any. Of course there will be exceptions to this, and the quality of the
synthesis results will vary from device to device, but generally it's good
or it's not.

.

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