Re: Generic synthesis target in Synplify Pro

"rnbrady" <rnbrady@xxxxxxxxx> wrote in message
news:1151584650.998970.110720@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
Hi folks

So, to tell whether my code is synthesizable, I have to do the
following:

1. Select a specific chip
2. Run the synthesis
3. Bring the mapped VHDL netlist file into ModelSim
4. Bring vendor specific files into ModelSim because they are required
by mapped file.
5. simulate for that chip.

Is there another way?

If your code is not synthesizable, you'll get stuck in the middle of stage
2. So steps 3-5 are not necessary to tell whether your code is
synthesizable. Did I miss something?

Generally, if code is synthesizable for one chip it is synthesizable for
any. Of course there will be exceptions to this, and the quality of the
synthesis results will vary from device to device, but generally it's good
or it's not.

Cheers,

-Ben-


.

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