Stopping the clock for power management
Hello,
For a low power application I would like to stop the clock feed into a FPGA
when enter ?sleep mode?. This is a common practice or can be dangerous? And
if is dangerous why? Maybe a silly question but I want to be sure about
that! I use Lattice XP parts.
Thanks,
Dan.
.
Relevant Pages
- Re: An FPGA startup is seeking testcase from potential customers
... The FPGA product it is developing has ultra low power consumption and ... is targeted to low power applications. ... and/or VHDL designs to test its software and FPGA architecture. ... a USB core, an Ethernet core, and a 32 Bit uC core, ...
(comp.arch.fpga) - Re: An FPGA startup is seeking testcase from potential customers
... The FPGA product it is developing has ultra low power consumption and ... is targeted to low power applications. ... and/or VHDL designs to test its software and FPGA architecture. ... a USB core, an Ethernet core, and a 32 Bit uC core, ...
(comp.arch.fpga) - Re: An FPGA startup is seeking testcase from potential customers
... Silicon Blue Technologies is an FPGA startup located in Sunnyvale CA. ... is targeted to low power applications. ... a USB core, an Ethernet core, and a 32 Bit uC core, ...
(comp.arch.fpga) - Re: Low Power CPU Implementation
... and I am designing for "as low power as possible". ... The Coolrunner II CPLD from Xilinx ... Real designs need some form of timebase, and FPGAs have no low power ... For very lowest power, you may want to remove the FPGA core Vcc, ...
(comp.arch.fpga) - An FPGA startup is seeking testcase from potential customers
... Silicon Blue Technologies is an FPGA startup located in Sunnyvale CA. ... The FPGA product it is developing has ultra low power consumption and ... is targeted to low power applications. ...
(comp.arch.fpga) |
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