Synplify prepending Z's to top level signal names in Verilog

From: jacob.bower@xxxxxxxxx
Date: 28 Jun 2006 12:01:39 -0700

Hi,

Does anyone know of a way to stop Synplify from pre-pending a "Z" to
names of top-level entity I/O signals which begin with an underscore
("_") when generating EDIF?

Thanks.
- Jacob

.

Follow-Ups:
- Re: Synplify prepending Z's to top level signal names in Verilog
  - From: John_H

Prev by Date: Spartan 3E, Output File
Next by Date: Virtex5 Availability
Previous by thread: Spartan 3E, Output File
Next by thread: Re: Synplify prepending Z's to top level signal names in Verilog
Index(es):
- Date
- Thread