Re: stimulus for FPGA
If you are new to FPGA, probably new to VHDL and Digital Design.
I hope you get some good references in Digital Systems, Synchronous
design and Synthesizable VHDL (google, the Great Library). You won´t
regret studying this and things will sound a lot more familiar...
Regards,
Ricardo
anand escreveu:
I am planning on buying either a Xilinx Spartan or Altera Development
Kit to test out some designs on FPGA. (I am New to FPGAs).
Question:
Once the design has been downloaded into the FPGA, how do I apply
stimulus and test the design? I believe several methods are possible,
but I would like one where both the stimulus (is applied in) and the
response (is checked) using a high level language like C or C++.
Are there any C/C++ "APIs" that allow the FPGA pins to be "wiggled"?
That way I can write C or C++ code to run a real "app".
.
Relevant Pages
- Re: Beginner Advice (Languages, tools etc.)
... Which I agree with in the sense that both the cpu and fpga can ... when developing for a cpu one is describing your design in C/C ... C and VHDL toolsets will be able to complete the C design in much less ... Hardware design skills are essential, ... (comp.arch.fpga) - Re: Series Termination
... reduced the trace width necessary for a particular transmission line. ... So far there is no useful output from the FPGA, ... much design there yet) and transmitted. ... loops with multiple caps on the supply lines. ... (sci.electronics.design) - Re: How big is my vhdl and am I approaching some size limitation on the chip.
... put you off going for FPGA. ... The Virtex range is ... ERROR:Cpld:1063 - Design requires at least 947 macrocells, ... (comp.arch.fpga) - Re: Why No Process Shrink On Prior FPGA Devices ?
... I understand the "Porsche" design philosophy and the apparant need to ... The rapid evolution of the silicon and underlying change in FPGA ... visibly superior tools, more FPGA IP, a quantum leap in productivity, ... (comp.arch.fpga) - Re: Getting started with FPGA
... The term 'compiler' means something different in HDL than in a programming language. ... Simulation is just that -- there's a tool that runs the HDL or that compiles it to a runnable program, that simulates the design on your workstation. ... There are open-source simulators out there, but the FPGA companies are pretty tight with their synthesis algorithms, so you won't find any open-source synthesizers. ... FPGA chip fixed onto the dev board and gets programmed in place? ... (comp.arch.fpga) |
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