Re: Virtex4 FX12 dynamic clock divider

Guru schrieb:

Here are some more details:
The output clock is used for CMOS imaging sensor.
The input clock can be 200MHz (CLK2X from DCM0)
Desired clock increment is about 1 MHz.
Maximum jitter not specified.

Ahhh, now we move forward!

2 DCMs free for now.

I think that DCM with dynamic FX ratios cannot produce such increments,
because
output frequency can only take fraction ratios according to input
clock. I think DDS is the best solution for my problem. The open
question is which frequency to take for input: 100, 200, 300 ..MHz?

Lets look at the worst case. You want 66 MHz max. If we use some kind of 660 MHz master clock, we will have 1/10 UI jitter. Not too bad, not too good. I guess for the CMOS image sensor the jitter wont hurt, since it is read like a ram array, isnt it?
So what you need is a multiphase DDS using lets say 4 accus. The MSBs must be parallel-serial converted using a x2 Clock and a DDR output stage. Been there, done that. Do a search in the FPGA FAQ, its explained there.

Regards
Falk
.

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