Re: Xilinx 3s8000?

On Mon, 08 May 2006 16:07:18 -0700, Ron <News5@xxxxxxxxxx> wrote:

Just for fun, here are the figures for a bus-width of 704 bits and 1024
bits.

Device utilization summary: (704 bit bus-width)
---------------------------
Selected Device : 3s500epq208-4
Number of Slices: 2592 out of 4656 55%
Number of Slice Flip Flops: 1779 out of 9312 19%
Number of 4 input LUTs: 4176 out of 9312 44%
Number of bonded IOBs: 18 out of 158 11%
Number of GCLKs: 1 out of 24 4%

Device utilization summary: (1024 bit bus-width)
---------------------------
Selected Device : 3s500epq208-4
Number of Slices: 2975 out of 4656 63%
Number of Slice Flip Flops: 2099 out of 9312 22%
Number of 4 input LUTs: 4896 out of 9312 52%
Number of bonded IOBs: 18 out of 158 11%
Number of GCLKs: 1 out of 24 4%


The amazing thing is that the slice and LUT counts seem to increase
*less* than the bus-width increases (ie; the size of the numbers it can
multiply). I've taken pains to ensure the optimizer isn't optimizing
something away that it shouldn't, so as far as I know these numbers are
correct.

The synthesizer reports a maximum frequency of 58MHz for the 64 bit
design, 16MHz for the 704 bit design, 12 MHz for the 1024 bit design "as
is" without any tweaking to improve the timing, so it should take about
1.1 microseconds to multiply two 64 bit numbers together, and 85
microseconds to multiply two 1024 bit numbers together.


Presumably you could do it rather quicker using the S3's multiplier blocks.....
.