Re: design optimization
- From: "Antti Lukats" <antti@xxxxxxxxxxxx>
- Date: Sun, 30 Apr 2006 20:39:53 +0200
<harikris@xxxxxxxxx> schrieb im Newsbeitrag
news:1146413671.605299.107260@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
Hi,there are almost no generic rules, but specially for PLDs the design for PLD
I am targeting the design for XC2C512 coolrunner device. That's the
biggest device i could find. Are you aware of any larger CPLD device?
I have a dual-edge triggered clock i.e i have no other CPLD choice
other than the coolrunner series.
I find that i am falling short of a dozen macrocell counts. The
fitter report says it needs 524 macrocells and i have 512 macrocells
available to me :-(
I have tried to optimize the design to my best possible knowledge (and
my knowledge is not that profound).
Can anybody here advise me on how to squeeze the design a LITTLE BIT
more
to make it fit into the XC2C512 device?
Thanks.
optimization
can yield in huge macrocell reduction.
if your current count is 524, then I would say with 99.9% that the desing
can be made
fit into 512 unless you have already spent over one man-month in PLD
specific optimization
to get the MC count down to 524.
the easiest way to find some resources is to find some block that are never
active at same time
and use 1 extra MC to flag for resource sharing
as example if you need counter and shift register but not at the same time
then almost all
MCs uses in counter and shift register could be shared.
besides that there are pretty many things for PLD that can influence the
design fit, but again
no golden rule for you, its all design specific and based on general 'it
doesnt fit' there is
little help that could be given to you
Antti
.
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- From: harikris
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