Re: Pull up resistors on Spartan 3 mode pins

Responses embedded - this is to underscore why I don't believe the information has been adequately digested, not because I feel an arguement is necessary. Trivial aspects of the design are not properly documented - that's been admitted - but the corrections have not been brought to our attention. So - trivially - what *did* I need to know about the JTAG interface that would have saved about 50 engineering hours and a change to a board that would have gone through a spin anyway? I'd sure like to know in case I end up designing with that part instead of the two XC3S1600Es on an upcoming board.

Peter Alfke wrote:
John, this is analog territory, and there is NOT just ONE right answer.

This could be digital territory but the analog aspects - pullups that are unaffected by HSWAP_EN - are forced upon the designers for pins - such as the JTAG - that no engineer should suspect would be pulled up by the silicon.

Obviously, a short circuit will always work, if you never need the pin
for any other purpose.
But we will not force you to do that, since you may have reasons not
to like it. It's a free country!
There is no mystery here, the purpose is only to establish a High
logic level. Nothing more, nothing less.
Obviously, a built-in pull-up resistor will establish a High logic
level, but it might be sensitive to crosstalk coming from your
pc-board..

And the Spartan3 devices have an explicitly low pullup impedance that should be virtually immune to any crosstalk that's applied to an unconnected pin. I'd expect the antenna of connecting a 10 kohm resistor to the internal 3 kohm pullup would introduce more noise than leaving the pin unconnected.

Obviously, any external resistor reduces the pull-up impedance, and
improves the situation.
Obviously an external pull-down resistor must be low enough in value to
overcome the internal pull-up resistance.

And I still favor a multimeter for getting a grip on fundamentals.

A multimeter is nice if a board that *isn't* strapped to VCC or GND is readily available - not usually the case when someone's designing their first board with this series of devices - but it still provides only an order of magnitude idea of what's happening on the pin. Tolerances on pullup and pulldown currents don't need to be tight so they aren't. I *will not* design a production board that relies on measurements to determine acceptable operation. The silicon *must* be tested to analog parameters that will guarantee operation in the board environment I design to.

I am all for clear documentation, but it never hurts to keep the
engineering mind alive.

An engineering mind is of little use when you have to submit to a design review with other engineers - some of which haven't designed with the device or know the documentation as thoroughly as someone who has - and must have documentation to support any action items produced from the review.

Compared to multi-gigabit receiver issues, this mode-pin level debate
is really a trivial subject.

Peter Alfke

Trivial subjects deserve trivial answers. There have been no answers that I have seen in these threads.
_____

Will the mode pins which appear to always have external pullups independent of the HWSWAP_EN pin behave fine when no external resistors are connected? Will the ~3kohm equivalent pullup impedances in unconnected pins work *just as well* or better than an external 4.7kohm pullup resistor to an imaginary mode pin with no internal pullup?

If the answer is "sure, no problem" where do we assure the fellow engineers that the pins will behave properly on power up (e.g., once the POR thresholds are passed, will those internal pullups have the full logic level established with internal pullups)? Is there a design issue such that POR from external pullups of nominal impedance willnot produce valid operation? Where could I possibly devine what the minimum pulldown resistor is to establish guaranteed behavior allowing an external jumper to change the mode pins?

These are trivial issues. With no documented answers. The last request from rickman was specifically - quoted in full:

rickman wrote:
> People here are driving me crazy insisting that the Xilinx factory has
> told them that you *MUST* tie the mode pins to either Vaux or GND.
> After finding all the info in the data *** and talking with support,
> it looks pretty clear to me that the S3 parts have a very stiff
> internal pull up and there is no need for an external pull up of any
> kind, resistor or direct connection to Vaux.
>
> Am I misunderstanding? Why did the factory tell us before that the
> mode pins *MUST* be tied to Vaux? Did we misunderstand what they were
> saying?
>
> I promise this is the last time I will ask about this. I am totally
> sick of going around this loop with everyone here.

Do you believe that the trivial answer *has* been fully illustrated by Steve Knapp or others in these threads?

There isn't a great desire to spend time and attention to trivial matters when there are problems like Multi-Gigabit transceivers out there. If we lose the trivial details, we lose the ability to design for error free production because of trivial misunderstandings.

All ricman wants is to get the fellow engineers off his back on a trivial issue. All I want is an understanding of how the pins behave that I connect for "trivial" functionality such as the JTAG pins that I *could not configure* to operate as part of a chain - I had to give the Spartan3 its own chain. The problems I had are probably trivial but I was unable to work past them without extreme measures.
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