Re: Spartan 3 chips in power up

rickman wrote:
Steve Knapp (Xilinx Spartan-3 Generation FPGAs) wrote:
The Spartan-3 resistor values turned out a bit stronger than originally
expected during design. The Spartan-3E resistors values are weaker,
but still strong enough to be useful. Early FPGA families has
resistors up around 20K to 50K, too weak to be useful.

Thanks for the info. I don't understand why you say a 50K PU is too
weak to be useful. That is more the range that I expect from an
internal PU. I am working the Spartan 3 configuration sequence and
have been getting a lot of coments from one person in particular about
my pull up/down resistors being too weak. He has made a lot of
unsubstantiated claims about a previous design not working until
various PU/PD resistors being replaced with 0 ohm jumpers. I see now
that there may be some truth to this.

I have been searching the data *** for all info on internal PU/PD and
it is not easy to find. It is rather scattered about and takes a lot
of searching. At first I didn't think any of the configuration pins
had PUs, but I saw the notation in Table 6 that the values of
resistance applied to User I/Os, Dual Purpose and Dedicated pins. So I
searched the document for pull-up and eventually found them all... I
think.

Here is what I think I have found...

HSWAP_EN - PU

PROG_B - PU during configuration, PU optional based on ProgPin config
option

DONE - bit stream configurable for open drain or totem-pole, optional
PU in User mode or external PU required

M0,M1,M2 - I am very confused about this one. Here is what it says
in the detailed pin description...
"In user mode, after configuration successfully completes, any levels
applied to these input are ignored. Each of the bitstream generator
options M0Pin, M1Pin, and M2Pin determines whether a pull-up resistor,
pull-down resistor, or no resistor is present on its respective mode
pin, M0, M1, or M2."

The mode pins have to be held in the appropriate state before any of
the bit stream can be loaded. So external PU/PDs are required.
Further the pins are ignored except for the rising edge of INIT_B.
Then what purpose does it serve to provide PU or PD after
configuration?

I am a bit confused about the setting of the Mode pins. There appears
to be a mode for JTAG configuration and in one place it says the JTAG
port can not be used until the INIT_B pins rises. But in another place
the data *** says "The JTAG port is always active and available
before, during, and after FPGA configuration." If this is true, do the
Mode pins need to be set to 101 to configure the part using JTAG? I
suppose it could be that the JTAG port is available for other things
like boundary scan, but not configuration unless the correct setting is
applied to the Mode pins. Do I need to provide for different settings
for JTAG configuration and Slave Parallel configuration? That would be
two resistors I need to change...

I don't know whether to feel stupid or to feel Xilinx is stupid. I
found an answer record that answers the part about the Mode pins having
pullups. I could not find anywhere in the data *** about the mode
pins having pullups. But the answer record says the Mode pins are all
pulled up to 2.5 volts by the equivalent of a 1.15 kohm resistor, worst
case. This means you need no larger than about 470 ohms for your pull
downs!!!

Does the data *** say these pins are pulled up and I missed it? I
actually did a search on "pull-up" (which is how Xilinx seems to term
them) and did not find any mention of a pullups on the mode pins. The
pin definition, where this info certainly should be, makes no mention
of this. I think Xilinx really dropped the ball on this one!

.