Re: Did National cheat with the Virtex 4? Or are they just smart engineers?

lecroy7200,

That is very funny: "do not allow..."

Excuse me, but I find that hilarious.

As if the FPGA Police will swoop down on you and have you arrested.

Right.

In the fine tradition of:

1) knowing that all components are designed to meet certain specifications
2) and that most of the elements of a design normally exceed the specifications
3) and that it may be that you are willing to sacrifice one specification over another (max frequency vs duty cycle)

engineers for decades have used components "outside" of their stated specifications.

The 'penalty' for being caught, is that the manufacturer may state that the usage is not covered by the specifications, and thus, not guaranteed.

Since the guarantee is just one of "take that part out, and replace it with another" the clever engineer has been taking advantage of their components for many years.

Of course, the clever engineer has to perform a complete verification and characterization on their own to be sure that suddenly the feature that they are using doesn't go away. For example: is the usage one that has wide margin, or is it very tight? How does the usage vary with voltage and temperature? Have you tested it on devices from different lots? Did you call or ask someone at the factory what their opinion was?

A very common practice is to buy commercial grade components. and qualify them yourself for an application that is not commercial grade.

Maybe you just need to go from -20C to +85C, and you know, as a reasonably intelligent engineer, that the I grade and C grade parts are pretty similar silicon, and all most of the difference is the test program. Since getting colder is usually not a problem with timing, or performance (at least is used to be, can't say that is true any longer), it is a safe bet to say that a C grade part will work fine at -20C?

Now the previous practice was pretty common, and I am not sure of how common that still is.

Getting back to the clock.

How fast do you want to go? What duty cycle distortion can you tolerate? Over what temperature range? How many do you need to make? Does it still meet the thermal Tj requirements? If it is found "to work" at room temp, and nominal voltages, looks like there is a lot more engineering that you have to do.

I have no idea what National did (haven't seen the presentation). I am sure it is all there in the documentation, as it has been pointed out. And, it sounds like they have a clock/4 option, which is just smart.

Enjoy.

Austin


lecroy7200@xxxxxxxx wrote:

I think I wrote DES in that last note, which would have been incorrect.


Austin,

Thanks for the input. Do you know if the parts are indeed running at
the 750MHz as stated in the video? Talking with Altera they also claim
the part was running in DDR mode, again not what the video shows. I
have tried to contact National about the design, but no luck yet.

"It won't be 45/55% like the spec *** says, but it will still have a
perfectly good pulse there. Obviously National is using this. Since
they are using it, that makes Xilinx kind of responsible for some
support of this application. "

I am not sure what the arrangement would be that Xilinx would be
responsible for what I would consider a bad design (assuming they
really are running the part at 750MHz). If Xilinx does plan to support
higher clock rates, what does this mean to me as a designer? Are there
any application notes that talk about overclocking the Virtex 4?

Just an FYI, if I try to do this same thing with the Stratix II and
Quartus, the tool will spit out an error. I spoke with Altera about
this and they made the comment that they do not allow the parts to be
over driven.

.