Re: Spartan 3 chips in power up

Steve Knapp (Xilinx Spartan-3 Generation FPGAs) wrote:
rickman wrote:
I have looked at the data *** and they say very clearly that the
Spartan 3 is held in reset until all three power supplies are fully up.
But the range of voltages is very wide, with reset being released when
the Vcoo on Bank four is as low as 0.4 volts.

I get a lot of grief from the FPGA firmware designers on every little
nit and pic that they don't like about the board design. I need to
know that this will keep the FPGA in reset and all IOs tristated
whether the various power voltages are above or below the internal
reset threshold, up to the point of being configured.

I assume that you are looking at Table 28 on page 54 in the Spartan-3
data ***.
http://www.xilinx.com/bvdocs/publications/ds099.pdf

These are essentially the trip points for the power-on reset (POR)
circuit inside the FPGA. The trip voltage range is somewhat wide due
to process variation, etc.

The POR circuit prevents configuration from starting until all three
power rails meet are within the trip-point range. The POR can happen
as early as the minimum voltage levels or as late as the maximum
limits.

Until the POR is released, all I/Os not actively involved in
configuration are high-impedance. The HSWAP_EN pin controls whether or
not internal pull-ups are applied to these I/Os. When HSWAP_EN = High,
the I/Os are turned off. Also, the pull-ups connect to their
associated power rail so you won't see the effect until VCCO ramps up.

Thanks for the info. Yes, I was looking at that table, plus table 30
on the next page. I am concerned about letting the DSP run before the
FPGA power is fully up and also operating the DSP while the FPGA power
has a momentary glitch for what ever reason. The DSP has a separate
core voltage from the FPGA and shares the Vcco of 3.3 volts. The FPGA
is configured and operated on the DSP external memory bus which also
connects to the program/data flash memory. I just want to make sure I
can defend my power up and power glitch operation of the board. When
the board is powering up, it is clear that the FPGA is held in reset
until the three power rails are somewhere within the trip ranges or
above. Then the DSP can hold the PROG_B signal low to continue holding
the FPGA in reset until the DSP is happy with the power supplies and is
ready to configure the FPGA without concern that the FPGA will mess up
the memory bus. That part seems clear.

But table 30 on page 55 seems to be saying that if Vccint or Vccaux dip
below the minimum values, but still above the reset trip points, the
configuration can be corrupted and the FPGA will not be put in reset.
In this case should I assume that the IOs can then be in any state and
may hang the DSP memory bus? If so, I need to use the PowerOK on the
LDO regulators to either halt the DSP or make sure it gets an NMI and
runs only from internal memory. I would prefer to be able to keep the
DSP running normally and record the power event in memory. I have some
concerns about the system power supply design and would like to be able
to show clear evidence that the power is not stable rather than having
to extrapolate from processor resets.

.

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