Re: Spartan 3 chips in power up


rickman wrote:
I have looked at the data *** and they say very clearly that the
Spartan 3 is held in reset until all three power supplies are fully up.
But the range of voltages is very wide, with reset being released when
the Vcoo on Bank four is as low as 0.4 volts.

I get a lot of grief from the FPGA firmware designers on every little
nit and pic that they don't like about the board design. I need to
know that this will keep the FPGA in reset and all IOs tristated
whether the various power voltages are above or below the internal
reset threshold, up to the point of being configured.

I assume that you are looking at Table 28 on page 54 in the Spartan-3
data ***.
http://www.xilinx.com/bvdocs/publications/ds099.pdf

These are essentially the trip points for the power-on reset (POR)
circuit inside the FPGA. The trip voltage range is somewhat wide due
to process variation, etc.

The POR circuit prevents configuration from starting until all three
power rails meet are within the trip-point range. The POR can happen
as early as the minimum voltage levels or as late as the maximum
limits.

Until the POR is released, all I/Os not actively involved in
configuration are high-impedance. The HSWAP_EN pin controls whether or
not internal pull-ups are applied to these I/Os. When HSWAP_EN = High,
the I/Os are turned off. Also, the pull-ups connect to their
associated power rail so you won't see the effect until VCCO ramps up.
---------------------------------
Steven K. Knapp
Applications Manager, Xilinx Inc.
General Products Division
Spartan-3/-3E FPGAs
http://www.xilinx.com/spartan3e
---------------------------------
The Spartan(tm)-3 Generation: The World's Lowest-Cost FPGAs.

.