Spartan 3 chips in power up

I have looked at the data *** and they say very clearly that the
Spartan 3 is held in reset until all three power supplies are fully up.
But the range of voltages is very wide, with reset being released when
the Vcoo on Bank four is as low as 0.4 volts.

I get a lot of grief from the FPGA firmware designers on every little
nit and pic that they don't like about the board design. I need to
know that this will keep the FPGA in reset and all IOs tristated
whether the various power voltages are above or below the internal
reset threshold, up to the point of being configured.

.

Quantcast