Re: USB Interface to Virtex-4


"Anonymous" <someone@xxxxxxxxxxxxx> wrote in message
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"Felix Bertram" <flx@xxxxxxxxxxxxxxxxxx> wrote in message
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I agree the software is complicated. (Way too complicated in my
opinion.)

if "software" is referring to the firmware: this is really not too
complicated. Have a look here:
* www.usb-by-example.com
* www.lvr.com

But all the solutions out there seem to be built around a little 8-bit
micro. You don't think it's silly to have a 10 million gate FPGA
sitting
next to an 8051?

disagreed. There are two types of data to be very clearly separated:

* asynchronous data: this is all the USB device enumeration and control
stuff. This is low bandwidth, most of it happens only during device
attachment, and this is quite simple. An 8051 is still too complex to
handle this, there are designs out there using a simple state machine.

* isochronous data: this is all the traffic your application requires.
In case you are streaming high bandwidth data and you need to do some
processing on it, an FPGA might be a good solution. You will usually not
want to pass 480Mbps of data through a CPU. Think of audio or video
applications, USB protocol analyzers, ...


Any comments welcome,
best regards,


Felix
--
Dipl.-Ing. Felix Bertram
http://www.bertram-family.com/felix

I guess my point was if you look at an fx2, for example, all I see is an
8-bit micro, a little bit of memory, and some relatively simple fifo
hardware. All of this seems trivial inside a virtex-4, yet most v4 designs
I've seen have the usb outside the fpga. Maybe that's so they can load the
fpga at power up but it seems like if they have flash memory anyway,
there's
no real advantage to usb outside the fpga.

-Clark



I have to admit that I find some of the replies to what I thought was a dumb
question a little odd. It's almost like some folks take personal offense at
the notion of using a couple hundred slices and a couple block rams to
implement a USB interface inside the FPGA. (The smallest V4fx has 12,000 lcs
and 36 brams) I think most of the counterarguments could apply to any other
peripheral: Why a uart? Why ethernet? Why even a PPC core when you can get a
better processor discretely?

If I had a solution that:
1. Integrated into EDK such that it adds like any other peripheral. The IP
should contain the micro, firmware, and the interface to the CPU.
2. Integrated into the board support package so that I can build my chip,
carry a few files over to my linux source and be able to compile it into the
linux kernel.
3. Stock linux and windows driver support.
4. Netusb compatibility such that I can take my usb master port and connect
it to any other port to create a network link.
5. USB1.1 initially but eventually 2.0.

I would gladly use it over any discrete solution that I constantly have to
worry about obscolecense or other supply problems, not to mention the extra
size, cost(part plus ordering plus handling), and power. Who hasn't had a
board build delayed because of a back order on some small part like a usb
chip?

-Clark




.

Relevant Pages

  • Re: USB Interface to Virtex-4
    ... You don't think it's silly to have a 10 million gate FPGA sitting ... applications, USB protocol analyzers, ... ... 8-bit micro, a little bit of memory, and some relatively simple fifo ... fpga at power up but it seems like if they have flash memory anyway, ...
    (comp.arch.fpga)
  • Re: USB Interface to Virtex-4
    ... But all the solutions out there seem to be built around a little 8-bit ... micro. ... If you really want a single chip "at all costs", then yes, pull the USB into the FPGA - the FPGA vendors will love you:) ... The USB uC's out there can directly, and correctly, drive the USB cable, and are proven to do so. ...
    (comp.arch.fpga)
  • Re: FPGA/DSP system design problem
    ... USB, FPGA works as a coprocessor, use FPGA's DSP, FPGA- ... DSP works as a coprocessor. ... I also need to store raw data, thus the data saving path will be ... FPGA, could DPRAM be implemented in FPGA? ...
    (comp.arch.fpga)
  • Re: FPGA/DSP system design problem
    ... The only thing I can say is that sharing the perpherial devices, (USB, ... internal to the FPGA. ... USB, FPGA works as a coprocessor, use FPGA's DSP, FPGA- ... The last question is FIFO vs. DPRAM, ...
    (comp.arch.fpga)
  • Re: Download the contents of the FPGAs RAM block
    ... But when I expand my design USB ... complicated would be to make use of the USB port on my FPGA. ... You might want to consider using chipscope pro, ... Chipscope will store your signals in real time ...
    (comp.arch.fpga)
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