comp.arch.fpga

• Date Index

---

• OPB Clocking Question, motty
• design optimization, harikris
  • Re: design optimization, Peter Alfke
    • Re: design optimization, Rob
      • Re: design optimization, Kolja Sulimma
      • Re: design optimization, Antti Lukats
  • Re: design optimization, Antti Lukats
  • Re: design optimization, Jim Granville
• Xilinx MPPR failing, GaLaKtIkUs?
• ML403 ZBT SRAM, GaLaKtIkUs?
• Xilinx PROM, maxascent
  • Re: Xilinx PROM, Steve Knapp (Xilinx Spartan-3 Generation FPGAs)
• FPGA Single LED Demos: FPGA board for a good ideas/suggestions, Antti Lukats
  • Re: FPGA Single LED Demos: FPGA board for a good ideas/suggestions, Hans
    • Re: FPGA Single LED Demos: FPGA board for a good ideas/suggestions, Ben Twijnstra
      • Re: FPGA Single LED Demos: FPGA board for a good ideas/suggestions, Antti Lukats
    • Re: FPGA Single LED Demos: FPGA board for a good ideas/suggestions, Antti Lukats
      • Re: FPGA Single LED Demos: FPGA board for a good ideas/suggestions, Austin Lesea
      • Re: FPGA Single LED Demos: FPGA board for a good ideas/suggestions, Antti Lukats
  • Re: FPGA Single LED Demos: FPGA board for a good ideas/suggestions, Jim Granville
    • Re: FPGA Single LED Demos: FPGA board for a good ideas/suggestions, Antti Lukats
      • Re: FPGA Single LED Demos: FPGA board for a good ideas/suggestions, Jim Granville
  • Re: FPGA Single LED Demos: FPGA board for a good ideas/suggestions, pbdelete
• Reset, Fizzy
  • Re: Reset, Peter Alfke
• Book Software for XC3190A?, tuxfriend
  • Re: Book Software for XC3190A?, Peter Alfke
    • Re: Book Software for XC3190A?, tuxfriend
      • Re: Book Software for XC3190A?, Josh Rosen
      • Re: Book Software for XC3190A?, Phil Hays
      • Re: Book Software for XC3190A?, tuxfriend
• Quartus and source control, avishay
  • Re: Quartus and source control, Petter Gustad
  • Re: Quartus and source control, johnp
  • Re: Quartus and source control, Subroto Datta
• URGENT: Xilinx site, GaLaKtIkUs?
  • Re: URGENT: Xilinx site, Leon
  • Re: URGENT: Xilinx site, Stephen Craven
    • Re: URGENT: Xilinx site, Gabor
      • Re: URGENT: Xilinx site, Peter Alfke
      • Re: URGENT: Xilinx site, Leon
• Re: DRC has announced its newest FPGA that drops into AMD's Socket 940, DJ Delorie
  • Re: DRC has announced its newest FPGA that drops into AMD's Socket 940, JJ
  • <Possible follow-ups>
  • Re: DRC has announced its newest FPGA that drops into AMD's Socket 940, DJ Delorie
    • Re: DRC has announced its newest FPGA that drops into AMD's Socket 940, JJ
• How to see *.vcd file outported from ChipScope from different computer, Weng Tianxiang
  • Re: How to see *.vcd file outported from ChipScope from different computer, ghelbig
  • Re: How to see *.vcd file outported from ChipScope from different computer, Hans
    • Re: How to see *.vcd file outported from ChipScope from different computer, Weng Tianxiang
• PCI bridge, Quazar
• Pull up resistors on Spartan 3 mode pins, rickman
  • Re: Pull up resistors on Spartan 3 mode pins, Antti
    • Re: Pull up resistors on Spartan 3 mode pins, John_H
      • Re: Pull up resistors on Spartan 3 mode pins, Antti
      • Re: Pull up resistors on Spartan 3 mode pins, Peter Alfke
  • Re: Pull up resistors on Spartan 3 mode pins, Jim Granville
    • Re: Pull up resistors on Spartan 3 mode pins, rickman
      • Re: Pull up resistors on Spartan 3 mode pins, Peter Alfke
      • Re: Pull up resistors on Spartan 3 mode pins, John_H
      • Re: Pull up resistors on Spartan 3 mode pins, Peter Alfke
      • Re: Pull up resistors on Spartan 3 mode pins, Jim Granville
      • Re: Pull up resistors on Spartan 3 mode pins, Peter Alfke
      • Re: Pull up resistors on Spartan 3 mode pins, Jim Granville
      • Re: Pull up resistors on Spartan 3 mode pins, Leon
      • Re: Pull up resistors on Spartan 3 mode pins, John_H
      • Re: Pull up resistors on Spartan 3 mode pins, Dave
      • Re: Pull up resistors on Spartan 3 mode pins, Jim Granville
      • Re: Pull up resistors on Spartan 3 mode pins, John_H
      • Re: Pull up resistors on Spartan 3 mode pins, Jeff Brower
      • Re: Pull up resistors on Spartan 3 mode pins, nospam
    • Re: Pull up resistors on Spartan 3 mode pins, rickman
  • Re: Pull up resistors on Spartan 3 mode pins, John Larkin
    • Re: Pull up resistors on Spartan 3 mode pins, rickman
    • Re: Pull up resistors on Spartan 3 mode pins, rickman
• please help me out, Lovely Robot
• Opteron HT coprocessors, JJ
  • Re: Opteron HT coprocessors, Rainer Buchty
    • Re: Opteron HT coprocessors, JJ
  • Re: Opteron HT coprocessors, c d saunter
    • Re: Opteron HT coprocessors, JJ
      • Re: Opteron HT coprocessors, c d saunter
• What would be the tariff classification of an FPGA development board?, jaxato
  • Re: What would be the tariff classification of an FPGA development board?, Rene Tschaggelar
    • Re: What would be the tariff classification of an FPGA development board?, jaxato
    • Re: What would be the tariff classification of an FPGA development board?, Philipp Klaus Krause
      • Re: What would be the tariff classification of an FPGA development board?, jaxato
      • Re: What would be the tariff classification of an FPGA development board?, Philipp Klaus Krause
• help me friend, kaps
• Xilinix SPI programming with USB Platform Cable, andrew . hood
  • Re: Xilinix SPI programming with USB Platform Cable, Antti
  • Re: Xilinix SPI programming with USB Platform Cable, Larry
    • Re: Xilinix SPI programming with USB Platform Cable, Antti
      • Re: Xilinix SPI programming with USB Platform Cable, Jim Granville
      • Re: Xilinix SPI programming with USB Platform Cable, Antti
• Bus macros compatible with ISE 8.1, Fabio Rodrigues de la Rocha
• Assigning MGT's in sample Aurora Design, billu
  • Re: Assigning MGT's in sample Aurora Design, colin
  • Re: Assigning MGT's in sample Aurora Design, sjulhes
  • Re: Assigning MGT's in sample Aurora Design, Paul Hartke
• initializing array of registers in XST, Jeff Brower
  • Re: initializing array of registers in XST, Brian Dam Pedersen
    • Re: initializing array of registers in XST, Jeff Brower
  • Message not available
    • Re: initializing array of registers in XST, Jeff Brower
  • Re: initializing array of registers in XST, Andy
• Xilinx SystemACE on multi-FPGA board, Stephen Williams
  • Re: Xilinx SystemACE on multi-FPGA board, Ed McGettigan
    • Re: Xilinx SystemACE on multi-FPGA board, Stephen Williams
      • Re: Xilinx SystemACE on multi-FPGA board, Ed McGettigan
      • Re: Xilinx SystemACE on multi-FPGA board, Stephen Williams
• Development Platform for begginer, gburx
  • Re: Development Platform for begginer, dc_rockclimbing
  • Re: Development Platform for begginer, Brian Drummond
    • Re: Development Platform for begginer, gburx
• System Generator, Fizzy
• CLock Issue, Fizzy
  • Re: CLock Issue, Ben Jones
    • Re: CLock Issue, Fizzy
      • Re: CLock Issue, Peter Alfke
      • Re: CLock Issue, John_H
    • Re: CLock Issue, Kantha
  • Re: CLock Issue, John_H
• LED Driver, pavithra . eswaran
  • Re: LED Driver, Antti
  • Re: LED Driver, Jim Granville
    • Re: LED Driver, Kolja Sulimma
      • Re: LED Driver, Jim Granville
• Xilinx: Prohibit propagation of timing constraint through a mux, Dolphin
  • Re: Xilinx: Prohibit propagation of timing constraint through a mux, Peter Alfke
    • Re: Xilinx: Prohibit propagation of timing constraint through a mux, Dolphin
  • Re: Xilinx: Prohibit propagation of timing constraint through a mux, Jeff Brower
  • Re: Xilinx: Prohibit propagation of timing constraint through a mux, jimwu88NOOOSPAM@xxxxxxxxx
• UCF-mode for Emacs, jimwu88NOOOSPAM@xxxxxxxxx
  • Re: UCF-mode for Emacs, Antti
  • Re: UCF-mode for Emacs, Andy Peters
• Synplify is not translating xilinx template for block ram, vssumesh
  • Re: Synplify is not translating xilinx template for block ram, Andy
    • Re: Synplify is not translating xilinx template for block ram, vssumesh
      • Re: Synplify is not translating xilinx template for block ram, John_H
      • Re: Synplify is not translating xilinx template for block ram, vssumesh
  • Re: Synplify is not translating xilinx template for block ram, Mike Treseler
• How are constants stored ?, Roger Bourne
  • Re: How are constants stored ?, Mike Treseler
    • Re: How are constants stored ?, Aurelian Lazarut
  • Re: How are constants stored ?, c d saunter
    • Re: How are constants stored ?, Roger Bourne
      • Re: How are constants stored ?, c d saunter
      • Re: How are constants stored ?, Ben Jones
  • Re: How are constants stored ?, Jon Elson
    • Re: How are constants stored ?, Aurelian Lazarut
      • Re: How are constants stored ?, Simon Peacock
• Xilinx PCI 64/32 bits IP, sjulhes
  • Re: Xilinx PCI 64/32 bits IP, John_H
    • Re: Xilinx PCI 64/32 bits IP, sjulhes
  • Re: Xilinx PCI 64/32 bits IP, Jeff Brower
    • Re: Xilinx PCI 64/32 bits IP, sjulhes
• Working Altera Byteblaster compatible design published under GPL, Antti
  • Re: Working Altera USB-Blaster compatible design published under GPL, Antti
    • Re: Working Altera USB-Blaster compatible design published under GPL, Amontec, Larry
      • Re: Working Altera USB-Blaster compatible design published under GPL, Antti
      • Re: Working Altera USB-Blaster compatible design published under GPL, Amontec, Larry
      • Re: Working Altera USB-Blaster compatible design published under GPL, Stephen Williams
      • Re: Working Altera USB-Blaster compatible design published under GPL, Antti
      • Re: Working Altera USB-Blaster compatible design published under GPL, Stephen Williams
      • Re: Working Altera USB-Blaster compatible design published under GPL, Antti Lukats
      • Re: Working Altera USB-Blaster compatible design published underGPL, Jim Granville
      • Re: Working Altera USB-Blaster compatible design published underGPL, Antti Lukats
      • Re: Working Altera USB-Blaster compatible design published underGPL, Eric Smith
      • Re: Working Altera USB-Blaster compatible design published underGPL, Antti Lukats
• Re: What is the best way to clock data in on one clock edge and out on another?, Ron
• OpenRisc 1200 on a XUP, karrelsj
  • Re: OpenRisc 1200 on a XUP, Javier Castillo
• The use of analog switches as level translators, Rene Tschaggelar
  • Re: The use of analog switches as level translators, langwadt
    • Re: The use of analog switches as level translators, Jim Granville
• Picoblaze C Compiler, Francesco
  • Re: Picoblaze C Compiler, Stephen Williams
    • Re: Picoblaze C Compiler, Mike Harrison
    • Re: Picoblaze C Compiler, Francesco
  • Re: Picoblaze C Compiler, bluetooth with FPGA
  • Re: Picoblaze C Compiler, Jim Granville
    • Re: Picoblaze C Compiler, Francesco
      • Re: Picoblaze C Compiler, Jim Granville
      • Re: Picoblaze C Compiler, electro
• PLB, Fizzy
• the problem when I design the udma33 interface, bjzhangwn
  • Re: the problem when I design the udma33 interface, Michael Schöberl
    • Re: the problem when I design the udma33 interface, bjzhangwn
• expanding multipliers, problem, Roger Bourne
  • Re: expanding multipliers, problem, Roger Bourne
  • Re: expanding multipliers, problem, John_H
  • Re: expanding multipliers, problem, Ray Andraka
    • Re: expanding multipliers, problem, Roger Bourne
• Virtex-4 MGTPower Distribution, Kolja Sulimma
• Spartan 3E Starter Board Question, Dave
  • Re: Spartan 3E Starter Board Question, John_H
• Re: 35$ supply 2 layers pcb prototype+2silk+2mask PCB(china), Aurelian Lazarut
  • Re: 35$ supply 2 layers pcb prototype+2silk+2mask PCB(china), njsldz@xxxxxxx
• Async FPGA ~2GHz, Jim Granville
  • Re: Async FPGA ~2GHz, Uwe Bonnes
    • Re: Async FPGA ~2GHz, Jim Granville
      • Re: Async FPGA ~2GHz, John_H
      • Re: Async FPGA ~2GHz, pbdelete
      • Re: Async FPGA ~2GHz, John_H
      • Re: Async FPGA ~2GHz, Peter Alfke
      • Re: Async FPGA ~2GHz, Jim Granville
      • Re: Async FPGA ~2GHz, Peter Alfke
      • Re: Async FPGA ~2GHz, David Brown
      • Re: Async FPGA ~2GHz, Peter Alfke
  • Re: Async FPGA ~2GHz, Bevan Weiss
    • Re: Async FPGA ~2GHz, dp
      • Re: Async FPGA ~2GHz, Austin Lesea
      • Re: Async FPGA ~2GHz, dp
      • Re: Async FPGA ~2GHz, Austin Lesea
      • Re: Async FPGA ~2GHz, dp
      • Re: Async FPGA ~2GHz, fpga_toys
      • Re: Async FPGA ~2GHz, Austin Lesea
      • Re: Async FPGA ~2GHz, fpga_toys
      • Re: Async FPGA ~2GHz, Jim Granville
      • Re: Async FPGA ~2GHz, fpga_toys
      • Re: Async FPGA ~2GHz, Austin Lesea
      • Re: Async FPGA ~2GHz, fpga_toys
      • Re: Async FPGA ~2GHz, Jim Granville
  • Re: Async FPGA ~2GHz, Bob Perlman
    • Re: Async FPGA ~2GHz, Peter Alfke
      • Re: Async FPGA ~2GHz, fpga_toys
      • Re: Async FPGA ~2GHz, Eric Smith
      • Re: Async FPGA ~2GHz, fpga_toys
      • Re: Async FPGA ~2GHz, Eric Smith
      • Re: Async FPGA ~2GHz, fpga_toys
      • Re: Async FPGA ~2GHz, Eric Smith
      • Re: Async FPGA ~2GHz, fpga_toys
      • Re: Async FPGA ~2GHz, Allan Herriman
      • Re: Async FPGA ~2GHz, fpga_toys
      • Re: Async FPGA ~2GHz, fpga_toys
      • Re: Async FPGA ~2GHz, Jim Granville
      • Re: Async FPGA ~2GHz, Symon
      • Re: Async FPGA ~2GHz, Eric Smith
      • Re: Async FPGA ~2GHz, Jim Granville
  • Re: Async FPGA ~2GHz, Josh Rosen
    • Re: Async FPGA ~2GHz, fpga_toys
• USB slot on Xilinx ML310 board - linux platform, chakra
• Xilinx Map vs IOB tri-state with clock enable..., johnp
  • Re: Xilinx Map vs IOB tri-state with clock enable..., johnp
• 116 warnings... successive approximation register using both phases of clock by spliting them, bad synchrounous assignment
  • Re: 116 warnings... successive approximation register using both phases of clock by spliting them, Sylvain Munaut
• clock multiplication, dancedynamix
  • Re: clock multiplication, Rene Tschaggelar
    • Re: clock multiplication, dancedynamix
      • Re: clock multiplication, unfrostedpoptart
      • Re: clock multiplication, Rene Tschaggelar
      • Re: clock multiplication, dancedynamix
      • Re: clock multiplication, Peter Alfke
  • Re: clock multiplication, John_H
• XST Internal error: VHDL constant record support, Andrew Greensted
  • Re: XST Internal error: VHDL constant record support, Ben Jones
    • Re: XST Internal error: VHDL constant record support, Andrew Greensted
      • Re: XST Internal error: VHDL constant record support, Ben Jones
• Xilinx ML401 Virtex 4 USB Peripheral, al99999
• Simulated Quartus II delays are much greater than measured, oopere
  • Re: Simulated Quartus II delays are much greater than measured, Kolja Sulimma
    • Re: Simulated Quartus II delays are much greater than measured, oopere
      • Re: Simulated Quartus II delays are much greater than measured, Jim Granville
      • Re: Simulated Quartus II delays are much greater than measured, Kolja Sulimma
  • Re: Simulated Quartus II delays are much greater than measured, oopere
• VERIFICATION AND TESTPLAN, AAA
  • <Possible follow-ups>
  • VERIFICATION AND TESTPLAN, AAA
  • VERIFICATION AND TESTPLAN, AAA
• Virtex 2 Config Times, Jerome
  • Re: Virtex 2 Config Times, John_H
  • Re: Virtex 2 Config Times, Austin Lesea
• SPARTAN3E SK LCD, Eka From Indonesia
  • Re: SPARTAN3E SK LCD, Steve Knapp (Xilinx Spartan-3 Generation FPGAs)
• FPGA with ASIC FPU units, Robin Bruce
  • Re: FPGA with ASIC FPU units, Rene Tschaggelar
• How to get divider in CRC32 , while implementatinh it in VHDL?, shailbadwaik
  • Re: How to get divider in CRC32 , while implementatinh it in VHDL?, Mike Treseler
• How to avoid lossing channel bonding when using Rocket IO?, king
  • Re: How to avoid lossing channel bonding when using Rocket IO?, Symon
  • Re: How to avoid lossing channel bonding when using Rocket IO?, colin
    • Re: How to avoid lossing channel bonding when using Rocket IO?, king
      • Re: How to avoid lossing channel bonding when using Rocket IO?, Ed McGettigan
      • Re: How to avoid lossing channel bonding when using Rocket IO?, king
      • Re: How to avoid lossing channel bonding when using Rocket IO?, Ed McGettigan
• Smallest uClinux configuration, Justin Erickson
  • Re: Smallest uClinux configuration, John Williams
• Opinions on Viva, ziggy
  • Re: Opinions on Viva, Kolja Sulimma
    • Re: Opinions on Viva, Ray Andraka
  • Re: Opinions on Viva, c d saunter
• Xilinx Virtex-4 OCM Usage Issues, charles . eddleston
  • Re: Xilinx Virtex-4 OCM Usage Issues, Andreas Ehliar
    • Re: Xilinx Virtex-4 OCM Usage Issues, charles.eddleston@xxxxxxxxx
  • Re: Xilinx Virtex-4 OCM Usage Issues, Ben Jones
    • Re: Xilinx Virtex-4 OCM Usage Issues, charles.eddleston@xxxxxxxxx
      • Re: Xilinx Virtex-4 OCM Usage Issues, Ben Jones
      • Re: Xilinx Virtex-4 OCM Usage Issues, charles.eddleston@xxxxxxxxx
      • Re: Xilinx Virtex-4 OCM Usage Issues, Ben Jones
      • Re: Xilinx Virtex-4 OCM Usage Issues, Brian Drummond
      • Re: Xilinx Virtex-4 OCM Usage Issues, Ben Jones
      • Re: Xilinx Virtex-4 OCM Usage Issues, Brian Drummond
      • Re: Xilinx Virtex-4 OCM Usage Issues, Andreas Ehliar
      • Re: Xilinx Virtex-4 OCM Usage Issues, charles.eddleston@xxxxxxxxx
• XDL router info needed, potter
• vhdl cpu emulator (any interest?), nkmlists
  • Re: vhdl cpu emulator (any interest?), ziggy
  • Re: vhdl cpu emulator (any interest?), Mike Treseler
  • Re: vhdl cpu emulator (any interest?), ghelbig
• Max and Argmax across 1,000 unsigned 10-bit numbers, andrewfelch
  • Re: Max and Argmax across 1,000 unsigned 10-bit numbers, Aurelian Lazarut
    • Re: Max and Argmax across 1,000 unsigned 10-bit numbers, andrewfelch
      • Re: Max and Argmax across 1,000 unsigned 10-bit numbers, Kolja Sulimma
      • Re: Max and Argmax across 1,000 unsigned 10-bit numbers, andrewfelch
• PLB communication, Fizzy
• Heating problem of the CPLD, john
  • Re: Heating problem of the CPLD, Austin Lesea
    • Re: Heating problem of the CPLD, john
      • Re: Heating problem of the CPLD, Austin Lesea
  • Re: Heating problem of the CPLD, John_H
  • Re: Heating problem of the CPLD, Rene Tschaggelar
  • Re: Heating problem of the CPLD, Jim Granville
  • Re: Heating problem of the CPLD, KJ
• Spartan 3 documentation confusing..., rickman
  • Re: Spartan 3 documentation confusing..., Austin Lesea
    • Re: Spartan 3 documentation confusing..., rickman
      • Re: Spartan 3 documentation confusing..., Austin Lesea
      • Re: Spartan 3 documentation confusing..., rickman
      • Re: Spartan 3 documentation confusing..., Austin Lesea
      • Re: Spartan 3 documentation confusing..., rickman
      • Re: Spartan 3 documentation confusing..., Austin Lesea
      • Re: Spartan 3 documentation confusing..., RobJ
      • Re: Spartan 3 documentation confusing..., John_H
      • Re: Spartan 3 documentation confusing..., Austin Lesea
      • Re: Spartan 3 documentation confusing..., David Brown
      • Re: Spartan 3 documentation confusing..., Peter Alfke
  • Re: Spartan 3 documentation confusing..., Antti Lukats
  • Re: Spartan 3 documentation confusing..., Steve Knapp (Xilinx Spartan-3 Generation FPGAs)
    • Re: Spartan 3 documentation confusing..., rickman
      • Re: Spartan 3 documentation confusing..., Michael Hennebry
      • Re: Spartan 3 documentation confusing..., rickman
      • Re: Spartan 3 documentation confusing..., Ulf Samuelsson
• ISE 8.1 Sub module Synthesis, Eli Hughes
  • Re: ISE 8.1 Sub module Synthesis, Zara
    • Re: ISE 8.1 Sub module Synthesis, Gerhard Hoffmann
      • Re: ISE 8.1 Sub module Synthesis, Zara
• Xilinx ISE Project Navigator bug, Roger Bourne
  • Re: Xilinx ISE Project Navigator bug, Mike Treseler
• comp.arch.reconfig, Robin Bruce
  • Re: comp.arch.reconfig, Mike Treseler
  • Re: comp.arch.reconfig, Symon
  • Re: comp.arch.reconfig, Sean Durkin
    • Re: comp.arch.reconfig, Robin Bruce
  • Re: comp.arch.reconfig, fpga_toys
    • Re: comp.arch.reconfig, Robin Bruce
      • Re: comp.arch.reconfig, fpga_toys
• regarding memories using megafunction wizard(altera), bachimanchi@xxxxxxxxx
  • Re: regarding memories using megafunction wizard(altera), ALuPin@xxxxxx
  • Re: regarding memories using megafunction wizard(altera), John_H
• Xilinx EDK 8.1 DDR controller behavior, Antti
  • Re: Xilinx EDK 8.1 DDR controller behavior, John
  • Re: Xilinx EDK 8.1 DDR controller behavior, Sylvain Munaut
    • Re: Xilinx EDK 8.1 DDR controller behavior, Antti Lukats
• ISE 8.1i for Linux ?, Jürgen Böhm
  • Re: ISE 8.1i for Linux ?, Dan McDonald
    • Re: ISE 8.1i for Linux ?, Daniel O'Connor
    • Re: ISE 8.1i for Linux ?, Eric Smith
      • Re: ISE 8.1i for Linux ?, Uwe Bonnes
      • Re: ISE 8.1i for Linux ?, Markus Kuhn
  • Re: ISE 8.1i for Linux ?, Bob Smith
    • Re: ISE 8.1i for Linux ?, Steve Knapp (Xilinx Spartan-3 Generation FPGAs)
• How to avoid this waring in ISE 8.1?, Devlin
  • Re: How to avoid this waring in ISE 8.1?, John_H
    • Message not available
      • Re: How to avoid this waring in ISE 8.1?, John_H
      • Re: How to avoid this waring in ISE 8.1?, Zara
• Microblaze & Linux tools., AnonymousFC4
  • Re: Microblaze & Linux tools. (repost), AnonymousFC4
    • Re: Microblaze & Linux tools. (repost), motty
    • Re: Microblaze & Linux tools. (repost), Austin Lesea
      • Re: Microblaze & Linux tools. (repost), AnonymousFC4
      • Re: Microblaze & Linux tools. (repost), Gob Stopper
      • Re: Microblaze & Linux tools. (repost), AnonymousFC4
      • Re: Microblaze & Linux tools. (repost), Austin Lesea
      • Re: Microblaze & Linux tools. (repost), John_H
• altera async fifo with different read/write port widths?, fpgabuilder
  • Re: altera async fifo with different read/write port widths?, Rob
• XST pre-defined macros, Jeff Brower
• Why Edge is required to read from Block RAM of V4, vssumesh
  • Re: Why Edge is required to read from Block RAM of V4, John_H
    • Re: Why Edge is required to read from Block RAM of V4, vssumesh
  • Re: Why Edge is required to read from Block RAM of V4, Peter Alfke
    • Re: Why Edge is required to read from Block RAM of V4, vssumesh
• More Xilinx S/W problems... ISE won't start, johnp
  • Re: More Xilinx S/W problems... ISE won't start, johnp
    • Re: More Xilinx S/W problems... ISE won't start, Terry Brown
• CAM, TCAM in Stratix, freechip
  • Re: CAM, TCAM in Stratix, Austin Lesea
  • Re: CAM, TCAM in Stratix, John_H
    • Re: CAM, TCAM in Stratix, freechip
      • Re: CAM, TCAM in Stratix, ALuPin@xxxxxx
      • Re: CAM, TCAM in Stratix, freechip
      • Re: CAM, TCAM in Stratix, John_H
      • Re: CAM, TCAM in Stratix, Mike Treseler
      • Re: CAM, TCAM in Stratix, John_H
      • Re: CAM, TCAM in Stratix, freechip
      • Re: CAM, TCAM in Stratix, John_H
• XST duplicate register option does not work, Brannon
  • Re: XST duplicate register option does not work, Gabor
• Xilinx Map & Physical Synthesis dies..., johnp
  • Re: Xilinx Map & Physical Synthesis dies..., Brannon
  • Re: Xilinx Map & Physical Synthesis dies..., Ben Jones
• XILINX : IBIS model creation, mohan
• Using another crystal oscillator.., aan.woodz@xxxxxxxxx
  • Re: Using another crystal oscillator.., rickman
• Video circle generator, Fred
  • Re: Video circle generator, Arlet
  • Re: Video circle generator, John_H
  • Re: Video circle generator, Ray Andraka
  • Re: Video circle generator, Ben Jones
    • Re: Video circle generator, Kolja Sulimma
  • Re: Video circle generator, Thomas Womack
  • Re: Video circle generator, Fred
• is Rocket io complaient with IEEE 802.3ae standard, syshen
• Bluetooth with FPGA?????, aymmmm@xxxxxxxxx
  • Re: Bluetooth with FPGA?????, Marc Randolph
  • Re: Bluetooth with FPGA?????, Mike Harrison
  • Re: Bluetooth with FPGA?????, Eric Smith
  • Re: Bluetooth with FPGA?????, Cristian CIRESSAN
• Raggedstone1 and Opencores PCI, John Adair
• problem with shift operation, Chandru . Kundagol
  • Re: problem with shift operation, Kantha
• Initializing array of BlockRAM instances in verilog, allanca
  • Re: Initializing array of BlockRAM instances in verilog, Gabor
    • Re: Initializing array of BlockRAM instances in verilog, Allan
      • Re: Initializing array of BlockRAM instances in verilog, Gabor
      • Re: Initializing array of BlockRAM instances in verilog, Allan
      • Re: Initializing array of BlockRAM instances in verilog, Gabor
• Editing Spartan3 DCM in FPGA(8.1.03) editor, Morten Leikvoll
  • Re: Editing Spartan3 DCM in FPGA(8.1.03) editor, Brian Davis
    • Re: Editing Spartan3 DCM in FPGA(8.1.03) editor, Morten Leikvoll
      • Re: Editing Spartan3 DCM in FPGA(8.1.03) editor, Brian Davis
• How to trsiate o/p pins?, srini
  • Re: How to trsiate o/p pins?, Martin Thompson
    • Re: How to trsiate o/p pins?, Gabor
• cheapest board (of any sort) with an Atmel At94k40 FPSLIC on it?, Adam Megacz
• An experience with Xilinx 8.1.02i, Weng Tianxiang
• fpga space estimate, Roger Bourne
  • Re: fpga space estimate, John_H
    • Re: fpga space estimate, Roger Bourne
      • Re: fpga space estimate, Austin Lesea
      • Re: fpga space estimate, John_H
      • Re: fpga space estimate, Roger Bourne
      • Re: fpga space estimate, John_H
  • Re: fpga space estimate, JJ
• Xilinx PCIe core vs. Icarus Verilog, Stephen Williams
  • Re: Xilinx PCIe core vs. Icarus Verilog, ghelbig
    • Re: Xilinx PCIe core vs. Icarus Verilog, Mike Treseler
• For those looking for the Spartan3E starter board..., John_H
• Synthesizer is creating unwanted global resources, vssumesh
  • Re: Synthesizer is creating unwanted global resources, Mike Treseler
    • Re: Synthesizer is creating unwanted global resources, vssumesh
      • Re: Synthesizer is creating unwanted global resources, Mike Treseler
      • Re: Synthesizer is creating unwanted global resources, vssumesh
      • Re: Synthesizer is creating unwanted global resources, vssumesh
      • Re: Synthesizer is creating unwanted global resources, Peter Alfke
      • Re: Synthesizer is creating unwanted global resources, vssumesh
      • Re: Synthesizer is creating unwanted global resources, vssumesh
• Xilinx OPB Arbiter, imp.chris
• OPB_SPI timing problems, Dolphin
• FPT'06 2nd call-for-papers, pinit . kum
• Reliability CPLD/FPGA vs Microcontroller, Falk Salewski
  • Re: Reliability CPLD/FPGA vs Microcontroller, Mike Treseler
    • Re: Reliability CPLD/FPGA vs Microcontroller, Slurp
  • Re: Reliability CPLD/FPGA vs Microcontroller, Jon Elson
    • Re: Reliability CPLD/FPGA vs Microcontroller, radarman
      • Re: Reliability CPLD/FPGA vs Microcontroller, Falk Salewski
      • Re: Reliability CPLD/FPGA vs Microcontroller, Kolja Sulimma
      • Re: Reliability CPLD/FPGA vs Microcontroller, Simon Peacock
      • Re: Reliability CPLD/FPGA vs Microcontroller, radarman
  • Re: Reliability CPLD/FPGA vs Microcontroller, Kolja Sulimma
    • Re: Reliability CPLD/FPGA vs Microcontroller, Falk Salewski
• XC9500XL Keeper - can it be disabled?, Peter C. Wallace
• XILINX 7.1 EDK Solaris 10, Michael Laajanen
• EDK : FSL macros defined by Xilinx are wrong, Sylvain Munaut
  • Re: EDK : FSL macros defined by Xilinx are wrong, Sylvain Munaut
    • Re: EDK : FSL macros defined by Xilinx are wrong, Austin Lesea
      • Re: EDK : FSL macros defined by Xilinx are wrong, Austin Lesea
      • Re: EDK : FSL macros defined by Xilinx are wrong, Sylvain Munaut
• Xilinx FPGA status after configuration., sabatini
  • Re: Xilinx FPGA status after configuration., John_H
    • Re: Xilinx FPGA status after configuration., sabatini
• XST issues with loop code, Jeff Brower
  • Re: XST issues with loop code, John_H
• Storing Variables into LMB Memory, Marco T.
• clock mux in spartan2e fpga, bjzhangwn
  • Re: clock mux in spartan2e fpga, JustJohn
    • Re: clock mux in spartan2e fpga, bjzhangwn
      • Re: clock mux in spartan2e fpga, Peter Alfke
      • Re: clock mux in spartan2e fpga, JustJohn
      • Re: clock mux in spartan2e fpga, JustJohn
• Is there anything fundamentally wrong with this code?, simon.stockton@xxxxxxxxxxxxxx
  • Re: Is there anything fundamentally wrong with this code?, Symon
    • Re: Is there anything fundamentally wrong with this code?, simon.stockton@xxxxxxxxxxxxxx
      • Re: Is there anything fundamentally wrong with this code?, Symon
      • Re: Is there anything fundamentally wrong with this code?, simon.stockton@xxxxxxxxxxxxxx
      • Re: Is there anything fundamentally wrong with this code?, KJ
  • Re: Is there anything fundamentally wrong with this code?, backhus
    • Re: Is there anything fundamentally wrong with this code?, simon.stockton@xxxxxxxxxxxxxx
• incremental synthesis xst ise 8.1, marcobuffa
• Multiple Independent Circuits on a Single FPGA, Dioptre
  • Re: Multiple Independent Circuits on a Single FPGA, Thomas Stanka
    • Re: Multiple Independent Circuits on a Single FPGA, Venkat
    • Re: Multiple Independent Circuits on a Single FPGA, Brannon
  • Re: Multiple Independent Circuits on a Single FPGA, radarman
    • Re: Multiple Independent Circuits on a Single FPGA, Thomas Stanka
      • Re: Multiple Independent Circuits on a Single FPGA, radarman
      • Re: Multiple Independent Circuits on a Single FPGA, Jon Elson
      • Re: Multiple Independent Circuits on a Single FPGA, Thomas Stanka
    • Re: Multiple Independent Circuits on a Single FPGA, Weng Tianxiang
      • Re: Multiple Independent Circuits on a Single FPGA, John_H
  • Re: Multiple Independent Circuits on a Single FPGA, Kolja Sulimma
• How is the max clock rate of a device fixed?, Ken Reeves
  • Re: How is the max clock rate of a device fixed?, Peter Alfke
    • Re: How is the max clock rate of a device fixed?, Symon
  • Re: How is the max clock rate of a device fixed?, Rene Tschaggelar
  • Re: How is the max clock rate of a device fixed?, John_H
• Viterbi IP Core, Venkat
• cannot be synthesized, bad synchronous description, Ingenrepons
• driving high speed ADC using an FPGA, Sanka Piyaratna
  • Re: driving high speed ADC using an FPGA, John_H
  • Re: driving high speed ADC using an FPGA, Ray Andraka
  • Re: driving high speed ADC using an FPGA, Venkat
    • Re: driving high speed ADC using an FPGA, Sanka Piyaratna
• MaxPlus2 and the Byteblaster MV, Rene Tschaggelar
  • Re: MaxPlus2 and the Byteblaster MV, Mike Treseler
  • Re: MaxPlus2 and the Byteblaster MV, chark . chen
    • Re: MaxPlus2 and the Byteblaster MV, Rene Tschaggelar
      • Re: MaxPlus2 and the Byteblaster MV, Lars
      • Re: MaxPlus2 and the Byteblaster MV, Rene Tschaggelar
• RIO Reference clock oscillator part, John
• FPGA availability & distribution options., pbdelete
  • Re: FPGA availability & distribution options., Gregory C. Read
  • Re: FPGA availability & distribution options., Rene Tschaggelar
  • Re: FPGA availability & distribution options., Fredrik
• blowfish encryption algorithm, chinmayshah.edi@xxxxxxxxxxxxxx
  • <Possible follow-ups>
  • blowfish encryption algorithm, chinmayshah.edi@xxxxxxxxxxxxxx
    • Re: blowfish encryption algorithm, ghelbig
• FPGA + FTDI, Eli Hughes
  • Re: FPGA + FTDI, Mike Harrison
  • Re: FPGA + FTDI, ammonton
  • Re: FPGA + FTDI, Steve Knapp (Xilinx Spartan-3 Generation FPGAs)
    • Re: FPGA + FTDI, Guru
• FPGA + MAC board?, pbdelete
  • Re: FPGA + MAC board?, Eli Hughes
  • Re: FPGA + MAC board?, damc4
  • Re: FPGA + MAC board?, Steve Knapp (Xilinx Spartan-3 Generation FPGAs)
  • Re: FPGA + MAC board?, Fredrik
• Implementation of cascadable shift register in virtex FPGA, prav
  • Re: Implementation of cascadable shift register in virtex FPGA, Gabor
  • Re: Implementation of cascadable shift register in virtex FPGA, John_H
• Virtex 4 Unbonded IOB, al99999
• How to connect FPGA and µC, Thomas Reinemann
  • Re: How to connect FPGA and µC, Mark McDougall
  • Re: How to connect FPGA and µC, Tim Wescott
  • Re: How to connect FPGA and µC, Mike Treseler
• ow to connect FPGA and µC, Thomas Reinemann
  • Re: ow to connect FPGA and µC, radarman
• Quartus SignalTap and bus turn around, Tommy Thorn
  • Re: Quartus SignalTap and bus turn around, Mark McDougall
    • Re: Quartus SignalTap and bus turn around, Tommy Thorn
• Xilinx DCI resistor placement guidelines, Andrew FPGA
  • Re: Xilinx DCI resistor placement guidelines, mr_dsp
    • Re: Xilinx DCI resistor placement guidelines, Austin Lesea
    • Re: Xilinx DCI resistor placement guidelines, Bob Perlman
      • Re: Xilinx DCI resistor placement guidelines, Andrew FPGA
      • Re: Xilinx DCI resistor placement guidelines, Andy
      • Re: Xilinx DCI resistor placement guidelines, Austin Lesea
• comparison with integer, Jeff Brower
  • Re: comparison with integer, Mike Treseler
    • Re: comparison with integer, Jeff Brower
• Wasn't the S3E board cost 149$@Xilinx , it's 178$@Avnet !!!!, Carsten
  • Re: Wasn't the S3E board cost 149$@Xilinx , it's 178$@Avnet !!!!, John_H
    • Re: Wasn't the S3E board cost 149$@Xilinx , it's 178$@Avnet !!!!, Carsten
      • Re: Wasn't the S3E board cost 149$@Xilinx , it's 178$@Avnet !!!!, John_H
      • Re: Wasn't the S3E board cost 149$@Xilinx , it's 178$@Avnet !!!!, John_H
  • Re: Wasn't the S3E board cost 149$@Xilinx , it's 178$@Avnet !!!!, Eric Smith
    • Re: Wasn't the S3E board cost 149$@Xilinx , it's 178$@Avnet !!!!, Carsten
• FLASH memory VHDL controller, PC
• PLD610, samiam
  • Re: PLD610, John_H
    • Re: PLD610, samiam
      • Re: PLD610, mk
      • Re: PLD610, samiam
      • Re: PLD610, Mike Treseler
      • Re: PLD610, Jim Granville
      • Re: PLD610, John_H
      • Re: PLD610, samiam
      • Re: PLD610, Eric Smith
      • Re: PLD610, radarman
      • Re: PLD610, Stephen Williams
      • Re: PLD610, samiam
      • Re: PLD610, Jim Granville
• Which is the best way to measure low frequencies?, Marco T.
  • Re: Which is the best way to measure low frequencies?, Jan Panteltje
  • Re: Which is the best way to measure low frequencies?, Peter Alfke
  • Re: Which is the best way to measure low frequencies?, Jim Granville
  • Re: Which is the best way to measure low frequencies?, Steve Knapp (Xilinx Spartan-3 Generation FPGAs)
  • Re: Which is the best way to measure low frequencies?, Marco T.
• INFO: *.XDL file, Superman
  • Re: INFO: *.XDL file, Martin Thompson
  • Message not available
    • Re: INFO: *.XDL file, Martin Thompson
• Virtex II Pro Config, maxascent
• How to apply timing constrains for large bus, vssumesh
  • Re: How to apply timing constrains for large bus, vssumesh
    • Re: How to apply timing constrains for large bus, John_H
      • Re: How to apply timing constrains for large bus, vssumesh
• Supply high quality pcb prototype(china), njsldz@xxxxxxx
• DCM Question, motty
• XST not inferring distributed RAM, Jeff Brower
  • Re: XST not inferring distributed RAM, JustJohn
    • Re: XST not inferring distributed RAM, Jeff Brower
• systemc, Ron Baker, Pluralitas!
  • Re: systemc, mk
    • Re: systemc, Ron Baker, Pluralitas!
      • Re: systemc, Hans
      • Re: systemc, Ron Baker, Pluralitas!
• Where is the xilinx online store gone?, jaxato
  • Re: Where is the xilinx online store gone?, Antti Lukats
    • Re: Where is the xilinx online store gone?, Peter Alfke
    • Re: Where is the xilinx online store gone?, Peter Alfke
      • Re: Where is the xilinx online store gone?, Jim Granville
      • Re: Where is the xilinx online store gone?, Jim Granville
      • Re: Where is the xilinx online store gone?, Mike Treseler
    • Re: Where is the xilinx online store gone?, Jim Granville
      • Re: Where is the xilinx online store gone?, jaxato
      • Re: Where is the xilinx online store gone?, Peter Alfke
      • Re: Where is the xilinx online store gone?, Alex Gibson
      • Re: Where is the xilinx online store gone?, Antti Lukats
      • Re: Where is the xilinx online store gone?, Mike Treseler
      • Re: Where is the xilinx online store gone?, Jan Panteltje
      • Re: Where is the xilinx online store gone?, Mike Harrison
      • Re: Where is the xilinx online store gone?, Brian Drummond
      • Re: Where is the xilinx online store gone?, Alex Gibson
  • Petition about the xilinx online store ?, Labo.EKO
    • Re: Petition about the xilinx online store ?, jaxato
      • Re: Petition about the xilinx online store ?, PC
      • Re: Petition about the xilinx online store ?, Antti Lukats
      • Re: Petition about the xilinx online store ?, jaxato
      • Re: Petition about the xilinx online store ?, Jon Elson
    • Re: Petition about the xilinx online store ?, Uwe Bonnes
      • Re: Petition about the xilinx online store ?, Mike Harrison
      • Re: Petition about the xilinx online store ?, PC
  • Re: Where is the xilinx online store gone?, Labo.EKO
    • Re: Where is the xilinx online store gone?, Labo.EKO
      • Re: Where is the xilinx online store gone?, Antti Lukats
      • Re: Where is the xilinx online store gone?, Peter Alfke
      • Re: Where is the xilinx online store gone?, Antti Lukats
      • Re: Where is the xilinx online store gone?, Kolja Sulimma
      • Re: Where is the xilinx online store gone?, Mike Harrison
      • Re: Where is the xilinx online store gone?, Kolja Sulimma
      • Re: Where is the xilinx online store gone?, Eric Smith
      • Re: Where is the xilinx online store gone?, circaeng
      • Re: Where is the xilinx online store gone?, Mike Harrison
      • Re: Where is the xilinx online store gone?, Jon Elson
• C# and Spartan 3 Starter Kit, Aaron
  • Re: C# and Spartan 3 Starter Kit, Eli Hughes
  • Re: C# and Spartan 3 Starter Kit, radarman
• Counting bits, andrewfelch
  • Re: Counting bits, Brannon
    • Re: Counting bits, andrewfelch
      • Re: Counting bits, Jan Panteltje
      • Re: Counting bits, Sylvain Munaut
      • Re: Counting bits, andrewfelch
      • Re: Counting bits, Kolja Sulimma
      • Re: Counting bits, andrewfelch
  • Re: Counting bits, Jan Panteltje
    • Re: Counting bits, andrewfelch
  • Re: Counting bits, Kolja Sulimma
  • Re: Counting bits, David M. Palmer
    • Re: Counting bits, news.verizon.net
  • Re: Counting bits, Michael Hennebry
  • Re: Counting bits, Thomas Womack
    • Re: Counting bits, andrewfelch
      • Re: Counting bits, JustJohn
      • Re: Counting bits, Michael Hennebry
      • Front Side Bus, was Re: Counting bits, JustJohn
• Spartan 3 chips in power up, rickman
  • Re: Spartan 3 chips in power up, ghelbig
  • Re: Spartan 3 chips in power up, Steve Knapp (Xilinx Spartan-3 Generation FPGAs)
    • Re: Spartan 3 chips in power up, rickman
      • Re: Spartan 3 chips in power up, Jim Granville
    • Re: Spartan 3 chips in power up, Jeff Brower
      • Re: Spartan 3 chips in power up, Jeff Brower
      • Re: Spartan 3 chips in power up, Peter Alfke
      • Re: Spartan 3 chips in power up, Steve Knapp (Xilinx Spartan-3 Generation FPGAs)
      • Re: Spartan 3 chips in power up, Jeff Brower
      • Re: Spartan 3 chips in power up, John_H
      • Re: Spartan 3 chips in power up, Steve Knapp (Xilinx Spartan-3 Generation FPGAs)
      • Re: Spartan 3 chips in power up, rickman
      • Re: Spartan 3 chips in power up, rickman
      • Re: Spartan 3 chips in power up, Jeff Brower
      • Re: Spartan 3 chips in power up, rickman
• Xilinx USB Platform Cable not working anymore (linux), Gerr
  • Re: Xilinx USB Platform Cable not working anymore (linux), Andreas Ehliar
    • Re: Xilinx USB Platform Cable not working anymore (linux), Gerr
• what wrong of this counter ?, kelvins
  • Re: what wrong of this counter ?, kelvins
    • Re: what wrong of this counter ?, Peter Alfke
      • Re: what wrong of this counter ?, kelvins
      • Re: what wrong of this counter ?, Peter Alfke
• Re: Cyclone II EP2C70 dev kits, where are they?, Karl
  • Re: Cyclone II EP2C70 dev kits, where are they?, Tommy Thorn
    • Re: Cyclone II EP2C70 dev kits, where are they?, Karl
      • Re: Cyclone II EP2C70 dev kits, where are they?, Tommy Thorn
• PROG_B and JTAG, Marco
  • Re: PROG_B and JTAG, Antti Lukats
• humble suggestion for Xilinx, John Larkin
  • Re: humble suggestion for Xilinx, John_H
    • Re: humble suggestion for Xilinx, John Larkin
  • Re: humble suggestion for Xilinx, KJ
    • Re: humble suggestion for Xilinx, John Larkin
  • Re: humble suggestion for Xilinx, Jim Granville
    • Re: humble suggestion for Xilinx, John Larkin
      • Re: humble suggestion for Xilinx, Jim Granville
      • Re: humble suggestion for Xilinx, John Larkin
  • Re: humble suggestion for Xilinx, Steve Knapp (Xilinx Spartan-3 Generation FPGAs)
    • Re: humble suggestion for Xilinx, John Larkin
• Problem: Invalid Processor Version Number 0x00000000- EDK-7.1- latest service pack, ML310, bootloop, download bitsream, chakra
  • Re: Problem: Invalid Processor Version Number 0x00000000- EDK-7.1- latest service pack, ML310, bootloop, download bitsream, chakra
• ARM Emulator, morpheus
  • Re: ARM Emulator, onyx49
  • Re: ARM Emulator, pbdelete
• Did National cheat with the Virtex 4, lecroy7200@xxxxxxxx
  • Re: Did National cheat with the Virtex 4? Or are they just smart engineers?, Austin Lesea
    • Re: Did National cheat with the Virtex 4? Or are they just smart engineers?, lecroy7200@xxxxxxxx
      • Re: Did National cheat with the Virtex 4? Or are they just smart engineers?, Austin Lesea
      • Re: Did National cheat with the Virtex 4? Or are they just smart engineers?, lecroy7200@xxxxxxxx
      • Re: Did National cheat with the Virtex 4? Doesn't look like it...., Austin Lesea
      • Re: Did National cheat with the Virtex 4? Doesn't look like it...., lecroy7200@xxxxxxxx
      • Re: Did National cheat with the Virtex 4? Or are they just smart engineers?, Eric Smith
  • Re: Did National cheat with the Virtex 4, Brian Davis
    • Re: Did National cheat with the Virtex 4, lecroy7200@xxxxxxxx
      • Re: Did National cheat with the Virtex 4, Brian Davis
      • Re: Did National cheat with the Virtex 4, lecroy7200@xxxxxxxx
      • Re: Did National cheat with the Virtex 4, Brian Davis
      • Re: Did National cheat with the Virtex 4, lecroy7200@xxxxxxxx
• RGMII mode on V4 Hard Tri-EMAC core, MM
  • Re: RGMII mode on V4 Hard Tri-EMAC core, Joseph Samson
    • Re: RGMII mode on V4 Hard Tri-EMAC core, MM
      • Re: RGMII mode on V4 Hard Tri-EMAC core, Joseph Samson
      • Re: RGMII mode on V4 Hard Tri-EMAC core, MM
      • Re: RGMII mode on V4 Hard Tri-EMAC core, Florian
      • Re: RGMII mode on V4 Hard Tri-EMAC core, MM
      • Re: RGMII mode on V4 Hard Tri-EMAC core, Florian
      • Re: RGMII mode on V4 Hard Tri-EMAC core, MM
      • Re: RGMII mode on V4 Hard Tri-EMAC core, Florian
      • Re: RGMII mode on V4 Hard Tri-EMAC core, Joseph Samson
• PCB Stack, maxascent
  • Re: PCB Stack, KJ
    • Re: PCB Stack, maxascent
      • Re: PCB Stack, Rene Tschaggelar
      • Re: PCB Stack, KJ
      • Re: PCB Stack, maxascent
      • Re: PCB Stack, Kolja Sulimma
      • Re: PCB Stack, jai.dhar@xxxxxxxxx
      • Re: PCB Stack, Kolja Sulimma
      • Re: PCB Stack, jai.dhar@xxxxxxxxx
      • Re: PCB Stack, John_H
      • Re: PCB Stack, KJ
    • Re: PCB Stack, MM
  • Re: PCB Stack, Joseph Samson
  • Re: PCB Stack, John_H
  • Re: PCB Stack, MM
• Urgent opening for US Onsite, kumar
  • Re: Urgent opening for US Onsite, John_H
• Published Verilog code: Timing improvement and FWFT FIFOs, Eli Billauer
• vertex II and powerpc core, Scott Willis
  • Re: vertex II and powerpc core, Ed McGettigan
    • Re: vertex II and powerpc core, Austin Lesea
      • Re: vertex II and powerpc core, Scott Willis
  • Re: virtex II and powerpc core, John_H
• Problem with Xilinx FTP, Hendra
  • Re: Problem with Xilinx FTP, Alan Nishioka
• Spartan3E readback, SPI programming, John_H
  • Re: Spartan3E readback, SPI programming, Antti
    • Re: Spartan3E readback, SPI programming, John_H
      • Re: Spartan3E readback, SPI programming, Alan Nishioka
      • Re: Spartan3E readback, SPI programming, John_H
      • Re: Spartan3E readback, SPI programming, Antti
      • Re: Spartan3E readback, SPI programming, John_H
      • Re: Spartan3E readback, SPI programming, Antti
      • Re: Spartan3E readback, SPI programming, John_H
      • Re: Spartan3E readback, SPI programming, Antti Lukats
      • Re: Spartan3E readback, SPI programming, John_H
      • Re: Spartan3E readback, SPI programming, Antti Lukats
      • Re: Spartan3E readback, SPI programming, John_H
      • Re: Spartan3E readback, SPI programming, Antti
      • Re: Spartan3E readback, SPI programming, Jim Granville
      • Re: Spartan3E readback, SPI programming, Alan Nishioka
      • Re: Spartan3E readback, SPI programming, John_H
  • Re: Spartan3E readback, SPI programming, Steve Knapp (Xilinx Spartan-3 Generation FPGAs)
• Print FAT table in a compact flash ??????????, sachink321
  • Re: Print FAT table in a compact flash ??????????, Alan Nishioka
  • Re: Print FAT table in a compact flash ??????????, Ray Andraka
• pci-express engineer, coutausse@xxxxxxxxx
• Spartan 3E Starter Kit is finally here!, Eric Smith
  • Re: Spartan 3E Starter Kit is finally here!, Steve Knapp (Xilinx Spartan-3 Generation FPGAs)
  • Re: Spartan 3E Starter Kit is finally here!, radarman
    • Re: Spartan 3E Starter Kit is finally here!, Scott Schlachter
  • Re: Spartan 3E Starter Kit is finally here!, John_H
• xilinx board xupv2p xc2v30 software dev. doubt, Prakash
• State Machine and Area Estimate Question, ssirowy@xxxxxxxxx
  • Re: State Machine and Area Estimate Question, Jim Granville
    • Re: State Machine and Area Estimate Question, ssirowy@xxxxxxxxx
• ISE 7.1 Map Error, Matt Fornero
• Altera Nios II & PCI Compiler 4.1.0 Question, Sander & Stieneke Odekerken
  • Re: Altera Nios II & PCI Compiler 4.1.0 Question, Nial Stewart
    • Re: Altera Nios II & PCI Compiler 4.1.0 Question, Sander & Stieneke Odekerken
• gemac, dhruvakshad
• spartan-3 starter kit board, jmariano
  • Re: spartan-3 starter kit board, Guru
    • Re: spartan-3 starter kit board, jmariano
• SPI Problem, Fizzy
• New Computing/Electronics Forum - Please Join!, matt . hoy
• timing constraints ?, Roger Bourne
  • Re: timing constraints ?, John_H
  • Re: timing constraints ?, JustJohn
    • Re: timing constraints ?, Bob Perlman
      • Re: timing constraints ?, Roger Bourne
• simulation of DCM blocks, vssumesh
  • Re: simulation of DCM blocks, vssumesh
• FPGA : Chip-scope + spartan-3e, bijoy
• xilinx XCVU2P-XC2VP30, Prakash
• To use adder and multiplier of DSP48 in V4, vssumesh
  • Re: To use adder and multiplier of DSP48 in V4, Sylvain Munaut <SomeOne@xxxxxxxxxxxxxx>
  • Re: To use adder and multiplier of DSP48 in V4, Ray Andraka
    • Re: To use adder and multiplier of DSP48 in V4, vssumesh
• want technical assistance in making toner chips, tonerchips
  • Re: want technical assistance in making toner chips, John_H
    • Re: want technical assistance in making toner chips, Symon
    • Re: want technical assistance in making toner chips, tonerchips
      • Re: want technical assistance in making toner chips, John_H
• Area Constraints in Xilinx, ssirowy@xxxxxxxxx
  • Re: Area Constraints in Xilinx, John_H
• very slow pull-up with CPLD design, shawnn
  • Re: very slow pull-up with CPLD design, Jim Granville
    • Re: very slow pull-up with CPLD design, Daniel Lang
• reading vhdl files, ace . shikha
  • Re: reading vhdl files, John_H
• Simulating TFT core in EDK, Jon
  • Re: Simulating TFT core in EDK, johnp
    • Re: Simulating TFT core in EDK, Jon
• Configuration Rate with multiple .bit files, Jeff Brower
  • Re: Configuration Rate with multiple .bit files, Alan Nishioka
    • Re: Configuration Rate with multiple .bit files, Jeff Brower
      • Re: Configuration Rate with multiple .bit files, Alan Nishioka
      • Re: Configuration Rate with multiple .bit files, Jim Granville
      • Re: Configuration Rate with multiple .bit files, Jim Granville
      • Re: Configuration Rate with multiple .bit files, Jeff Brower
• Interfacing to DDS v5.0 in System Generator, Ira Thorpe
• Distributed Arithmetic, nimayshah
  • Re: Distributed Arithmetic, nimayshah
    • Re: Distributed Arithmetic, Peter Alfke
      • Re: Distributed Arithmetic, nimayshah
  • Re: Distributed Arithmetic, Symon
  • Re: Distributed Arithmetic, Nial Stewart
• NTSC video capture, Matt Fornero
  • Re: NTSC video capture, Anonymous
• Very basic question, Fizzy
  • Re: Very basic question, John_H
    • Re: Very basic question, Tommy Thorn
      • Re: Very basic question, kulkarku
• code, shereen.ahmed
• ROM resource sharing, mikel
  • Re: ROM resource sharing, John_H
    • Re: ROM resource sharing, mikel
      • Re: ROM resource sharing, John_H
• location constraint doubt, Prakash
  • Re: location constraint doubt, John_H
• Register Map coding style, gretzteam
• LDPC, shereen.ahmed
  • Re: LDPC, Antti
• unused pins, Prakash
  • Re: unused pins, bjzhangwn
    • Re: unused pins, motty
    • Re: unused pins, Prakash
• How to handle the high fanout, hitsx@xxxxxxxxxx
  • Re: How to handle the high fanout, bjzhangwn
  • Re: How to handle the high fanout, Ralf Hildebrandt
  • Re: How to handle the high fanout, hitsx@xxxxxxxxxx
• get the data from tranceiver, Arun
• xilinx JTAG, Prakash
  • Re: xilinx JTAG, Aurelian Lazarut
    • Re: xilinx JTAG, Prakash
      • Re: xilinx JTAG, Aurelian Lazarut
• 8:1 MUX implementaion in XILINX and ALTERA, prav
  • Re: 8:1 MUX implementaion in XILINX and ALTERA, Ben Jones
    • Re: 8:1 MUX implementaion in XILINX and ALTERA, Kolja Sulimma
      • Re: 8:1 MUX implementaion in XILINX and ALTERA, Mike Hutton
• xilinx DCM Timing warning, prakash.na@xxxxxxxxx
  • Re: xilinx DCM Timing warning, Gabor
    • Re: xilinx DCM Timing warning, Prakash
• New FPGA Technology Reaches New Heights, bsmithtech
• Creating macros, Superman
• Re: DDR SDRAM Controller, ada
• www.buswares.com, water9580@xxxxxxxxx
  • Re: www.buswares.com, burn . sir
    • Re: www.buswares.com, water9580@xxxxxxxxx
  • Re: www.buswares.com, Isaac Bosompem
• decoding, shereen.ahmed
• asynchronous FIFO design, kelvins
  • Re: asynchronous FIFO design, Peter Alfke
    • Re: asynchronous FIFO design, Peter Alfke
  • Re: asynchronous FIFO design, Brian Philofsky
• C-Compiler for free VHDL controller core ?, Peter Winkler
  • Re: C-Compiler for free VHDL controller core ?, Isaac Bosompem
    • Re: C-Compiler for free VHDL controller core ?, Tommy Thorn
      • Re: C-Compiler for free VHDL controller core ?, Antti
      • Re: C-Compiler for free VHDL controller core ?, Peter Winkler
      • Re: C-Compiler for free VHDL controller core ?, Antti Lukats
      • Re: C-Compiler for free VHDL controller core ?, Ulf Samuelsson
    • Re: C-Compiler for free VHDL controller core ?, Peter Winkler
  • Re: C-Compiler for free VHDL controller core ?, burn . sir
    • Re: C-Compiler for free VHDL controller core ?, Antti Lukats
  • Re: C-Compiler for free VHDL controller core ?, Philipp Klaus Krause
  • Re: C-Compiler for free VHDL controller core ?, Peter Winkler
    • Re: C-Compiler for free VHDL controller core ?, Jim Granville
    • Re: C-Compiler for free VHDL controller core ?, Francesco
      • Re: C-Compiler for free VHDL controller core ?, Peter Winkler
• DDR Termination, maxascent
  • Re: DDR Termination, Bob
• Compiler to FPSLIC, Niels Sandmann
  • Re: Compiler to FPSLIC, Ralf Hildebrandt
    • Re: Compiler to FPSLIC, Niels Sandmann
  • Re: Compiler to FPSLIC, Adam Megacz
    • Re: Compiler to FPSLIC, Niels Sandmann
  • Re: Compiler to FPSLIC, Mike Treseler
    • Re: Compiler to FPSLIC, Niels Sandmann
  • Re: Compiler to FPSLIC, Tim Wescott
    • Re: Compiler to FPSLIC, Niels Sandmann
      • Re: Compiler to FPSLIC, Tim Wescott
      • Re: Compiler to FPSLIC, Jim Granville
  • Re: Compiler to FPSLIC, Jim Granville
    • Re: Compiler to FPSLIC, Niels Sandmann
      • Re: Compiler to FPSLIC, Jim Granville
    • Re: Compiler to FPSLIC, Niels Sandmann
      • Re: Compiler to FPSLIC, Jim Granville
  • Re: Compiler to FPSLIC, jetmarc
    • Atmel FPSLIC, Adam Megacz
      • Re: Atmel FPSLIC, jetmarc
      • Re: Atmel FPSLIC, Adam Megacz
• Why does Synplify add clock buffers?, burn . sir
  • Re: Why does Synplify add clock buffers?, Duane Clark
    • Re: Why does Synplify add clock buffers?, burn . sir
      • Re: Why does Synplify add clock buffers?, Duane Clark
  • Re: Why does Synplify add clock buffers?, Alan Myler
• FPGA FAQ and the spam problem, burn . sir
  • Re: FPGA FAQ and the spam problem, Jeremy Stringer
  • Re: FPGA FAQ and the spam problem, ziggy
  • Re: FPGA FAQ and the spam problem, Philip Freidin
    • Re: FPGA FAQ and the spam problem, burn . sir
      • Re: FPGA FAQ and the spam problem, Bob Perlman
  • Re: FPGA FAQ and the spam problem, Mike Treseler
• Help needed, Fizzy
  • Re: Help needed, motty
    • Re: Help needed, Fizzy
      • Re: Help needed, motty
• who know what is the problem, zhangxun0501
  • <Possible follow-ups>
  • who know what is the problem, zhangxun0501
    • Re: who know what is the problem, Ray Andraka
• what is architectural diffrence between block ram & distributed ram?, kulkarku
  • Re: what is architectural diffrence between block ram & distributed ram?, John_H
• shared BRAM between PPC and FPGA fabric, amit
  • Re: shared BRAM between PPC and FPGA fabric, Joseph
  • Re: shared BRAM between PPC and FPGA fabric, MM
• one question for a error of map, zhangxun0501
• Re: Virtex-4 RocketIO and G.709 OTU-2, Chris Clark
  • <Possible follow-ups>
  • Re: Virtex-4 RocketIO and G.709 OTU-2, Chris Clark
  • Re: Virtex-4 RocketIO and G.709 OTU-2, Chris Clark
  • Re: Virtex-4 RocketIO and G.709 OTU-2, CsquaredPhD
  • Re: Virtex-4 RocketIO and G.709 OTU-2, Gerhard Hoffmann
    • Re: Virtex-4 RocketIO and G.709 OTU-2, mike_la_jolla
      • Re: Virtex-4 RocketIO and G.709 OTU-2, GaLaKtIkUs?
    • Re: Virtex-4 RocketIO and G.709 OTU-2, Allan Herriman
• C H S in a Compact flash, sachink321
  • Re: C H S in a Compact flash, pbdelete
  • Re: C H S in a Compact flash, Ray Andraka
• Accessing compact flash?????????, sachink321
  • Re: Accessing compact flash?????????, John Williams
  • Re: Accessing compact flash?????????, Eli Hughes
    • Re: Accessing compact flash?????????, Jan Panteltje
  • <Possible follow-ups>
  • Accessing compact flash?????????, sachink321
  • Accessing compact flash?????????, sachink321
    • Re: Accessing compact flash?????????, Ray Andraka
      • Re: Accessing compact flash?????????, sachink321
      • Re: Accessing compact flash?????????, Ray Andraka
      • Re: Accessing compact flash?????????, sachink321
      • Re: Accessing compact flash?????????, Ray Andraka
• rather simple gsr Q, Roger Bourne