design compiler optimization

From: mahalingamv@xxxxxxxxx
Date: 30 Mar 2006 19:01:15 -0800

Hi,

Does synopsys design compiler perform a TILOS based circuit
optimization.

TILOS is a iterative circuit sizing tool, published in 1985 by fishburn
and dunlop.

any information and details about this is requested.

thanks,

Mahalingam

.

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