Re: Xilinx hi-speed interconnect/routing question

Johnp,

The simple answer is, no, we don't publish the information you are asking for, as we have practically no reason to support 'hand crafted' designs (results in too many unhappy people -- been there, done that).

Does the path in question span a BRAM column? That would be one reason for the difference.

Generally, differences are real, and we know they are there, and they are ususally there for a very good reason (that is the way it was in layout).

The "accepted" way of doing this, is to create a macro or block with its own contstraints, hard fixed or relatively fixed, and let the tools place it properly...but I admit that doing that is tough to fight the tools to squeeze ps out of a design. Resorting to FPGA_Editor, and just placing it exactly where it belongs and works is easier. It is just hell to support, and maintain.

There are many on this forum who know how to squeeze and navigate, and do what you need done, but I suspect they get paid for that knowledge...

Austin

johnp wrote:

I'm working on a V2Pro design that needs to have a small
portion operate at over 400 MHz. As I've looked into the
timing, I've noticed that similar routing between slices
seems to have different timing delays. For example:

Location Delay type Delay(ns)

-------------------------------------------------
SLICE_X34Y1.YQ Tcko 0.374

SLICE_X34Y3.BY net (fanout=1) 0.614
SLICE_X34Y3.CLK T*** 0.202

-------------------------------------------------
Total 1.190ns

**************************************************

Location Delay type Delay(ns)

-------------------------------------------------
SLICE_X66Y42.YQ Tcko 0.374

SLICE_X66Y44.BY net (fanout=1) 0.407
SLICE_X66Y44.CLK T*** 0.202

-------------------------------------------------
Total 0.983ns

Note that both circuites route from a YQ output, jump two slices,
then go to a BY input. Yet, the net delays vary by 200 psec.

Ideally, I'd pack the 2 flip-flops in one slice, but in my design they
are clocked by opposite clock edges as I convert a DDR signal from
the negedge into the posedge domain.

Can anyone explain the difference in interconnect delay? Does
Xilinx publish anything that really explains how to get the
shortest routing delay?

Thanks!

John Providenza

.