Re: for all those who believe in ASICs....

Take two ... bad google day ...

Phil Hays wrote:
If you don't understand the problem, you are not very likely to come
up with a solution.

Quite true.

Something quite like this was tried. Some very good reasons not to do
it were found, the hard way. "Human beings, who are almost unique in
having the ability to learn from the experience of others, are also
remarkable for their apparent disinclination to do so." (Douglas
Adams)

One of the most remarkable forms of success, is the difficult
challenges offered from failures.

I'm sure Douglas Adams would agree. But you wouldn't like it.

You probably will not like the contradiction that it poses either:

a) Experienced team A works diligently, ending in a heroic failure

b) Team B offers regular help, which is turned down

c) after the failure is complete, Team B completes the project
quickly.

Should Team B have accepted the failure as hard fact that the problem
had no viable solution, and also failed by failing to try? (IE learning
from Team A's failure)

In 30 years of being self employed I've made about 20% of my income
from taking over failed projects with a low bid no risk flat fee
proposals to management ... no delivery, no payment. All I have at risk
is my time and my reputation to always succeed on those projects.
Several of those projects were taken from experienced teams that I
offered friendly help on a regular basis, and was turned down. Others I
took after one or more other companies failed to deliver what the
client needed, often with sharp adivice that I would be doomed to
repeating the cycle.

Ever figure out what current a wafer full of die would draw? Now for
the fun part. How to get all that current to all the die without too
much voltage drop? Oh, and what if one die is in latchup?

yep ... and did you notice the part of the proposal about using on
wafer power control for each die?

I thought you were not going to use an ATE.

Did you notice the part of the proposal about using ATE for screening
dangrous defects, like shorted power nets?

Some things can't be implemented on wafers. Disk drives, relays,
precision resisters, ...

None of which are needed on die for self testing.

As long as test coverage is way less than 50%, sure.

You have already given up if you think that. The explict idea behind
defect managment is functional issolation by designing for 100% test
coverage at some level of detail. Either a route, FF, LUT, buffer, or
other resource fails testing, or is presumed operational, and to be
screened if necessary by using redundant logic in the system level
design initially.

I suspect that this will be an itterative process of incremental
refinement over a long period of time, maybe at first only saving
40-60% of the reject yield, and possibly progressing to nearly all. I
suspect one of the most important parts of the process will be design
refinements to prevent/issolate the failure impacts on future designs,
increasing both the primary and secondary yields in the long term.

One interesting form of "success" includes not reaching the entire
objective, but leaving a carefully documented road map of the
challenges, assumptions, and proposed solutions along the way so that
those that follow have a better defined path to chip away at.

Now, I don't know how much of Xilinx's yield is scrap today, or would
be scrap at the end of 6 months, a year or two years. I do suspect the
number will steadily decrease using design for defect management
strategies.

I do know the "cost" to Xilinx to sell scrap die and packaged product
is pretty low, if it comes with a long term partnership to provide
engineering input to increase yields for both zero defect, and managed
defect segments. The long term promise of such a program is for each
to act in good faith to increase revenues for both partners as the
process matures.

I believe that I can create products which are defect aware using the
largest Xilinx parts, that presumably also have the largest percentage
of rejects. I'm willing to invest the engineering into developing a
recovery process, if Xilinx is willing to provide scrap material, and
include in that partnership an agreement to share data and design
suggestions to improve yeilds. As the recovery process becomes
profitable, there is certainly incentives on both parties part to share
that windfall. That's a pretty low risk deal for Xilinx if they are
crushing scrap in die and packaged form today.

.

Relevant Pages

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