Re: DCM question

You had better look at your DSP data sheet and see what clock the external
bus timing parameters are referenced to. In my design (similar to yours),
there were no timing specs between the DSP bus signals and the DSP clock
input; the specs referred to the DSP's bus clock output. So I had to send
the oscillator to the DSP clock input, and the DSP clock output to the FPGA.

"Marco" <marco@xxxxxxxxxxx> wrote in message
news:1141806772.500591.65390@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
Hi,
for my project I'd like to use the same 25MHz clock signal (coming from
an external oscillator) for both the DSP and my Spartan3. A pll inside
the DSP creates the 600MHz clock from the 25MHz. I still don't know how
fast I'll let the FPGA work, so I was supposed to acquire the 25MHz
clock and through a DCM bring it to the level, i.e. 50MHz or 60Mhz,
that optimizes my design. In such a way I would have the same clock for
both my devices, syncronized and each with its proper frequency.
Can I do that or should I avoid this way of working?
Is it a common way to work?
Suggestions?
Thanks, Marco



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