Re: DCM question

On 8 Mar 2006 00:32:52 -0800, "Marco" <marco@xxxxxxxxxxx> wrote:

for my project I'd like to use the same 25MHz clock signal (coming from
an external oscillator) for both the DSP and my Spartan3. A pll inside
the DSP creates the 600MHz clock from the 25MHz. I still don't know how
fast I'll let the FPGA work, so I was supposed to acquire the 25MHz
clock and through a DCM bring it to the level, i.e. 50MHz or 60Mhz,
that optimizes my design. In such a way I would have the same clock for
both my devices, syncronized and each with its proper frequency.
Can I do that or should I avoid this way of working?
Is it a common way to work?
Suggestions?

I don´t know the exact way the DSP creates the 600 MHz, but my best
suggestion would be to use the DCM to go up from 25MHz to 50 or 60 MHz
(whichever fits you best), and then output this signal to the DSP, so
that it derives its internal clock from the one generated by the FPGA.
You may even need to feedback the clock to the FPGA.

Thus way, you may have a better control of the phase between both
devices, and the inter-clock jitter will be limited to that coming
from the DSP, the other way you might get more jitter as both the
devices would put their own contribution.

Maybe there are better solutions, but you must first analyse the
synthesiser and DCM parameters, and how they will fit together.

Regards,
Zara
.

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