Re: Simple ADS5273 -> Xilinx Interconnect Model

John,

Good SI analysis is so critical these days; it's nice to see
someone else's results.

I wouldn't consider those "results" yet, more of a "preliminary model".

But I have used those attenuators in several real-world designs.

I have also done similar models in the past, and after a round
of lab verification, additions, and tweaking, they worked far
better than the Xilinx IBIS LVDS models/Hyperlynx of the time.

And just try modeling SSO, noise injection from DCI modulation,
and other such beasties with your typical combination of IBIS
model/simulator versions and feature support.


Is the ADS5273 a non-standard LVDS "style" of driver?

The appellation "LVDS" has been applied to many parts
that swing to LVDS levels into a 100 ohm load, but don't
have the expected back termination or driver design.

IIRC, 40-140 ohm Rdiff was expected in one of the
early LVDS standards.

Unless I'm misinterpreting the ADS5273 data***,
the part is NOT back terminated:

Differential Output Impedance : 13 kohm

"The single-ended output impedance of the LVDS
drivers is very high because they are current-source
driven. If there are excessive reflections from the
receiver, it might be necessary to place a 100 ohm
termination resistor across the outputs of the LVDS
drivers to minimize the effect of reflections."


The lack of back termination that you included in the
"normal" LVDS driver makes me wonder if the greater problem
is with the ADS5273 rather than the non-ideal FPGA input.

As I suggested in the 527x thread, I suspect TI
intentionally avoided the internal back termination
to avoid coupling the unpredictable and ugly reflections
off your typical FPGA input back into the analog stuff.

The reflection arrival time is not under the control
of the A/D chip designer, unlike the internal sequencing
of the front end sampler and output driver switching,
and the incoming reflections might hit say 50-60% of the
original output step amplitude.


A technique used in telecomm systems that might be helpful for probing:
rather than using a large attenuator between Rx and Tx with the raw probe
point somewhere along the transmission line, consider using a
reduced-amplitude probe point.

Good point, I didn't mention probes or probe loading models.
I'll try to keep a list of things to add to that document.

At 840 Mbps, a decent active or Zo probe should work fine.
I did have some notes on probing in one of the reference links;
I've copied them below.

I've also used broadband resistive couplers and power splitters
for really fast stuff like OC192.

If only this were microwave, I could break out the directional
couplers and isolators :)

Brian


From [Ref 2]
http://groups.google.com/group/comp.arch.fpga/msg/a044806f313848e6

Also, in most high speed systems, there is a need to monitor
the link in some fashion, either as part of a system jitter/skew
or setup/hold verification, or perhaps a non-intrusive signal
tap for operational monitoring.

This is often done by placing a passive resistive coupler
in-line with the signal, or perhaps probe pads for one of the
low-loading differential active probes.

If the tap is placed close to the highly capacitive receiver
input, the ringback can leave the differential signal in limbo
at the probe point ( both inputs within the differential Vih/Vil
hysteresis switching threshold ) until the reflected pulse has
passed; if you place it farther up the line, the reflection can
re-clock the probe, or interfere with the next incoming bit.

.