Re: tricks to make large PLAs fast?

Eric Smith wrote:
Jim Granville <no.spam@xxxxxxxxxxxxxxxxx> writes:

That's a large array - does it really cover 2^25 combinations,
or can you compress the inputs, so that the remainder can fit into
Block Ram(s) ?


Not really. It was a design originally implemented in custom CMOS in
the early 1980s, and I don't really want to redesign it any more than
necessary. There are lots of don't cares scattered throughout the
AND matrix of the PLA, so it won't fit in any reasonable-sized ROM
or RAM. Also, the 25-bit input words don't uniquely map to outputs;
a given input word may (and often does) match multiple product terms.

.... another idea : you could target a CPLD, like XC2C512, and see what that tool flow makes of it. It may give some ideas...

Their PLA has a fanin of 40, a depth of 49 per 16 MC block, so it
_should_ be very efficent - but it may be too big for the tools
to optimize properly, in which case some middle nodes might help ?
-jg

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