Re: Virtex-4 RAMB16 relative placement

Because of comments from others on this forum, I've gotten into the habit of
LOCing the BlockRAMs whenever relative placement is critical. While there
might be a slightly "better" location for the BlockRAMs than what I choose,
the place & route seems to do a better job filling the logic around the
memory rather than trying to figure out a good placement for both logic and
memory at the same time.

"sudheer" <ksudheerkumar@xxxxxxxxx> wrote in message
news:1141033138.838815.238520@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
XST is synthesising the following verilog code to a 8192x24-bit RAM.

<code snipped>

ISE is mapping this 8192x24bit RAM to 12 RAMB16s. But when the device
is occupying about 65% resources (with other modules integrated) the
RAMs are not placed as neighbors leading to different timing problems
on different compilations.

The requirement is to allow the ISE-map to place these RAMs closely,
either in a column or controlled rectangular array of RAMB16s, after
which PAR can place this group optimally anywhere in FPGA based on
other modules.

I am not able to use RLOC or RLOC_RANGE constraints to accomplish this.
Kindly let me know how to control the relative placement of RAMB16s.

Thank you and I await your inputs/ suggestions ASAP.
K Sudheer Kumar


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