Re: FPGA: Model-SIm XE problem
- From: Duane Clark <dclark@xxxxxxxxxxxx>
- Date: Mon, 27 Feb 2006 16:42:12 GMT
Duane Clark wrote:
bijoy wrote:Hi I have made a generic component like below
entity fifo is generic( AW : integer; PROG_EMPTY_THD :
std_logic_vector(AW downto 0);...
The problem is that you are using AW within the generic declaration area. The way you are doing that is a bit unusual too. Make PROG_EMPTY_THD a signal instead of a generic, and the problem should go away.
Oops, and of course also PROG_FULL_THD.
.
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- Re: FPGA: Model-SIm XE problem
- From: Duane Clark
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