Virtex-4 RAMB16 relative placement

XST is synthesising the following verilog code to a 8192x24-bit RAM.

module bram_8k (clk, addr, di, do);
input clk;
input [12:0] addr;
input [23:0] di;
output reg [23:0] do;

reg [23:0] ram [8191:0];

always@(posedge clk) begin
ram[addr] <= di;
do <= ram[addr];
end

endmodule

ISE is mapping this 8192x24bit RAM to 12 RAMB16s. But when the device
is occupying about 65% resources (with other modules integrated) the
RAMs are not placed as neighbors leading to different timing problems
on different compilations.

The requirement is to allow the ISE-map to place these RAMs closely,
either in a column or controlled rectangular array of RAMB16s, after
which PAR can place this group optimally anywhere in FPGA based on
other modules.

I am not able to use RLOC or RLOC_RANGE constraints to accomplish this.
Kindly let me know how to control the relative placement of RAMB16s.

Thank you and I await your inputs/ suggestions ASAP.
K Sudheer Kumar

.

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