Re: FPGA: Model-SIm XE problem
- From: "ALuPin@xxxxxx" <ALuPin@xxxxxx>
- Date: 27 Feb 2006 01:12:45 -0800
hi bijoy ,
you could declare AW or even different AW (AW1, AW2, AW3 ...)
in a separate package (which could also be used for synthesis of
course)
By doing so Modelsim should have no
problems to identify the length of the std_logic vector in the
corresponding instantiation.
Rgds
André
.
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