Re: Implementing a two-modulus PLL divider in Altera Stratix II


I am therefore trying to build a so-called "two-modulus prescaler"
PLL. In other words, I would like to use the FPGA's internal logic
in order to build a frequency divider that toggles between
division by N and division by N-1. By adjusting the duty cycle
of the divider toggling signal, I should be able to achieve
output frequencies corresponding to high-resolution factional
frequency multiplication factors. The toggling frequency
should obviously be well above the PLL's loop filter bandwidth.
I believe I can achieve the required divisor resolution with
32-bit counters.

What's the spectrum of the output of a "two-modulus prescaler"?

What's the spectrum of a DDS?

How low do I have to make the PLL bandwidth if I want to filter
out the junk? (Assume I run the DDS output through a PLL
to filter out the steps.)

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