Re: using FPGA in control field


"wicky" <wicky.zhang@xxxxxxxxx> wrote in message
news:1139670926.240198.163270@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
Hi all,

I want to use FPGA in control field. I know that uC or DSP processor is
a preferable choice to control engineer in general. But in my opinion,
the HDL-based logic inside FPGA is more appropriate for those high
performance needed but simple function tasks just as the role of a
controller in control system, while the C language can realize
complicated application. i.e. In my control system, the controller
will be based on HDL inside FPGA to get a extremely high performance
and high reliability, while the rest of the work, such as
communication, data processing and human-machine interface will be
based on C language to get a more flexible system.

Certainly, the C-based embedded system may be implemented inside FPGA
to form a SOC system and may be based on an OS for more convinent.

Can anyone give me some advice and papers about this idea? thans a
lot.

Best Regards,

Wicky


I did this recently using only an FPGA, with no host CPU. As you suggest,
the FPGA is great for creating high performance control functions (in my
case the performance wasn't high - just a phase controlled SCR drive, but
things like feedback filtering, PLL's for synchronizing, etc etc)

Since I had no host, I also implemented a communications protocol for a
tuning and monitoring application hosted on a PC - I really wouldn't
recommend this, such things are much easier in a processor.

One piece of advice - if you can afford it, use an FPGA with embedded
multiplier blocks and plentiful RAM. In pretty much all control functions
you're MAC'ing process variables and coefficients. In my design, I ate up
most of an EP1C6 with multipliers. You can reduce this somewhat by creating
long multipliers, or off-line calculation of LUT's for partial products, but
on my next design (way bigger and multi-channel servo performance), I'm
moving to Cyclone II just for the embedded multipliers.

Another thing that makes it somewhat harder on an FPGA than in MCU/DSP is
implementing all the "what if" non-linear cases that are easy to code in C
or assembler (simple example, avoid integral wind-up when some down-stream
process saturates). Saturation versus overflow is also something that DSP's
help you with. You will have to create saturating maths blocks.

With all the caveats, you can achieve some pretty breathtaking loop closure
times - not that you usually need them.

G




.

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