Re: Async Processors


rickman wrote:
Again, depends on the application. If it's a packet routing/switching
engine
running below wire speed, then it means that the device will
route/switch
more packets per second without overrunning when not worst case.

Do they design the equipment to drop packets when it gets hot or when
the PSU is near the low margin or when the chip was just not the
fastest of the lot? That is my point. You design equipment to a level
of acceptable performance. The equipment spec does not typically
derate for uncontrolled variables such as temperature, voltage and
process.

Yes, nearly every communications device with a fast pipe, will discard
packets when over run. Cisco Routers of all sizes, DSL modems,
wireless radios, .... it's just everyday fact of life.

Faster cpu's cost more money ... if you want to by a Cisco router that
drops packets at higher loads, spend more money. The primary difference
between whole families, is simply processor speed.

If your VOIP started dropping packets so that your phone calls were
garbled and the provider said, "of course, we had a hot day, do you
expect to see the same speeds all the time?", would you find that
acceptable?

IT HAPPENS!!! Reality Check ... IT HAPPENS EVERY DAY.


You can do the same thing with a clocked design. Measure the
temperature and run the clock faster when the temperature is cooler.
It just is not worth the effort since you can't do anything useful with
the extra instructions.

But that only allows derating for temp based on worst case assessment
of the process data. It doesn't allow for automatic adjustments for
process
variation or other device specific variances.

Actually they do. That is called speed grading and nearly all makers
of expensive CPU chips do it. You could do that with any chip if you
wanted to. But there is no point unless you want to run your Palm 10%
faster because it is a toy to you.

No, that is a completely different issue ... not dynamic fit of
processing
power to current on chip delays.

Yes, I agree, you have to be realistic. There is no significant
advantage to having a processor run at different speeds based on
uncontrolled variables.

No ... wrong.

Sorry ... that is true only in your mind for your designs. It does not
apply
broadly to all designs for all real world problems. Real engineers do
this because it really does matter for THEIR designs.

So, I've already stated clearly one every day application where the
customer
benifits by having routers only drop packets when the hardware isn't
capable
of going faster, rather than derating the whole design to reduced worst
case
performance levels.

Not true, as there have always been ways to design without glitches
using choices like gray coded counters for state machines, one hot
state machines, and covering the logic states to be glitch free by
design, which most good engineers will purposefully do when practical
and necessary, as should good tools. It's just a design decision to
ensure that every term is deterministic without static or dynamic
hazards. Maybe they don't teach this in school any more now that
everyone does vhdl/verilog.

You are talking about stuff that no one uses because there is very
little advantage and it does not outweight the cost. My point is that
none of this is justified at this time.

"no one uses because" ... sorry, but clearly you haven't been keeping
up with your reading and professional skills training as you certainly
don't know everyone.

You really need to read a lot more the C.A.F. to get a better grounding
on what people actually do these days. ... For starters read starting
at the end of page 3 about Data path reordering and glitch power
reduction:

http://www.sequencedesign.com/downloads/90300-368.pdf

Get the point ... people concerned about low power, do actually design
to remove glitching by design ... by serious engineering design. Keep
on reading about what "no one uses because" to get a real understanding
about real no body engineering for power in section 5 Architecture
Optimization:

http://www.mrtc.mdh.se/publications/0914.pdf

Note the lead in to the topic ... glitches can consume a large amount
of power. Now clearly some engineers have never had to worry about
battery life or waste heat from excess power. But for the real power
sensitive engineers, the truth is that nobody can ignore these factors.

The reality is that the faster the logic gets, the more you have to
worry about these timing miss match effects. Three generations back, a
1ns glitch was obsorbed into the switching times. At 90nm glitches as
short as a few dozen ps will cause two unwanted transistions and power
loss. The whole problem with glitches is this extra double state flip
when there should have been zero that robs power ... and that is
amplified by all the logic behind the glitch also flipping once or
twice as well ... greatly amplifing the cost of the initial failure to
avoid glitches by design. At 90nm there are a whole lot more sources of
glitches that require attention to design details that didn't even
matter two or three generations back. So while you may think that no
one actually attempts glitch free design practices, by using formal
logic tools to stop them dead, you clearly do not know everyone to make
that statement so firmly.

If you still think that no one decides to design formally correct
glitch free circuits, keep
reading what leading engineers from Actel, Xilinx, say:


http://klabs.org/mapld04/tutorials/vhdl/presentations/low_power_techniques.ppt
http://www.ece.queensu.ca/hpages/faculty/shang/papers/fpga02.pdf

Note the end of section 5.2 where it discusses the power consumed in
several of the designs sections due to glitches was 9-18%. Note also
that agressively pipelining with the additional "free" registers in
FPGA's is a clear win. Other ASIC studies by Shen on CMOS combinatorial
logic have stated that as much as 20-70% of a devices power can be
consumed by glitches, which is a strong reminder to use the FPGA
registers and pipeline wisely.

So, from my perspective "no one" concerned about power can possibly be
doing their job if they are unware of glitching power issues ... a
stark contrast from your enlightening broad statements to the contrary.

http://www.interfacebus.com/Design_Logic_Timing_Hazards.html
http://findatlantis.com/absint_extended.pdf

I have never heard anyone suggest that you should design to avoid the
intermediate transients of logic. Of course you can, but there are
very few designs indeed that need to be concerned about the last few %
of power consumption this would save.

I think you have now, and it's a lot more than a few percent for some
designs.

Great, you have identified an advantage of async designs. They can be
done with extremely fine grained dual rail logic that can avoid
transients in intermediate logic. But then you can do that in sync
designs if you decide you want to, right?

yep ... with worst case limited performance too.

.

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