Re: Async Processors


rickman wrote:
Can you explain? I don't see how you can async clock logic without
having a delay path that exceeds the worst path delay in the logic.
There is no way to tell when combinatorial logic has settled other than
to model the delay.

Worst case sync design requires that the clock period be slower than
the
longest worst case combinatorial path ... ALWAYS ... even when the
device is operating under best case conditions. Devices with best case
fab operating under best case environmentals, are forced to run just as
slow as worst case fab devices under worst case environmental.

The tradeoff with async is to accept that under worst case fab and
worst
case environmental, that the design will run a little slower because of
the
ack path.

However, under typical conditions, and certainly under best case fab
and
best case environmentals, the expecation is that the ack path delay
costs
are a minor portion of the improvements gained by using the ack path.
If
the device has very small deviations in performance from best case to
worst case, and the ack costs are high, then there clearly isn't any
gain
to be had. Other devices however, do offer this gain for certain
designs.

Likewise, many designs might be clock constrained by an exception path
that is rarely exercised, but the worst case delay for that rare path
will
constrain the clock rate for the entire design. With async, that
problem
goes away, as the design can operate with timings for the normal path
without worrying about the slowest worst case paths.

I think you are talking about a pretty small effect compared to the
overall power consumption.

Depends greatly on the design and logic depth. For your design it might
not make a difference as you suggest. For a multiplier it can be
significant,
as every transistion, including the glitches cost the same dynamic
power.

.

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