comp.arch.fpga

• Date Index

---

• FPGA communication, I2C and DAC, redstripe
• XUP Vertex II J5 Expansionheader Voltage, Ludwig Lenz
  • Re: XUP Vertex II J5 Expansionheader Voltage, Antti
• PPC Linux SoC on Virtex4 in 4 hours !?, Antti
  • Re: PPC Linux SoC on Virtex4 in 4 hours !?, Ivan
    • Re: PPC Linux SoC on Virtex4 in 4 hours !?, Antti Lukats
• conv_integer, Marco T.
  • Re: conv_integer, ALuPin@xxxxxx
    • Re: conv_integer, Marco T.
      • Re: conv_integer, Michael Schöberl
  • Re: conv_integer, John Adair
• 32 bit select map, pilwoochun@xxxxxxxxxx
• New XC9572 decoupling newbie question :-), :-)
  • Re: New XC9572 decoupling newbie question :-), PeteS
    • Re: New XC9572 decoupling newbie question :-), Benjamin Todd
      • Re: New XC9572 decoupling newbie question :-), :-)
  • Re: New XC9572 decoupling newbie question :-), PeteS
• Observed a bug in the Model sim V 6.0a, vssumesh
• System crashes when configuring altera stratix pci board, MT
  • Moreover, the fpga hangs even when I configure a very simple design too..., MT
  • Re: System crashes when configuring altera stratix pci board, Nial Stewart
• PCI configuration for ML310, igelado@xxxxxxxxx
  • Re: PCI configuration for ML310, John Williams
    • Re: PCI configuration for ML310, igelado@xxxxxxxxx
      • Re: PCI configuration for ML310, John Williams
• NGCBUILD .. MDT error on Virtex 4, Cog_Rad_link
  • Re: NGCBUILD .. MDT error on Virtex 4, Paul Hartke
• VirtexII routing data widths, Chris Francis
  • Re: VirtexII routing data widths, Antti
    • Re: VirtexII routing data widths, Chris Francis
• Virtex-4 RAMB16 relative placement, sudheer
  • Re: Virtex-4 RAMB16 relative placement, John_H
• Re: FPGA: Model-SIm XE problem, ALuPin@xxxxxx
  • <Possible follow-ups>
  • Re: FPGA: Model-SIm XE problem, Duane Clark
    • Re: FPGA: Model-SIm XE problem, Duane Clark
  • Re: FPGA: Model-SIm XE problem, Mike Treseler
• Serious problem with XST, Matthias Alles
  • Re: Serious problem with XST, sudheer
    • Re: Serious problem with XST, young
      • Re: Serious problem with XST, Matthias Alles
• tricks to make large PLAs fast?, Eric Smith
  • Re: tricks to make large PLAs fast?, John Adair
    • Re: tricks to make large PLAs fast?, Eric Smith
  • Re: tricks to make large PLAs fast?, Brian Drummond
    • Re: tricks to make large PLAs fast?, Eric Smith
  • Re: tricks to make large PLAs fast?, John_H
  • Re: tricks to make large PLAs fast?, Jim Granville
    • Re: tricks to make large PLAs fast?, Eric Smith
      • Re: tricks to make large PLAs fast?, Jim Granville
      • Re: tricks to make large PLAs fast?, Eric Smith
      • Re: tricks to make large PLAs fast?, Jim Granville
      • Re: tricks to make large PLAs fast?, Kolja Sulimma
  • Re: tricks to make large PLAs fast?, Michael Hennebry
• miniuart, zhangweidai
  • Re: miniuart, Martin Schoeberl
    • Re: miniuart, David Brown
  • Re: miniuart, kcl
    • Re: miniuart, zhangweidai
      • Re: miniuart, John Adair
      • Re: miniuart, cs_posting
      • Re: miniuart, zhangweidai
      • Re: miniuart, John Adair
      • Re: miniuart, zhangweidai
• Re: C Manual for Microblaze Software, Karel
• Coregen ISE 6.1, foag
  • Re: Coregen ISE 6.1, Barry Brown
• ERROR:MapLib:482, Mich
  • Re: ERROR:MapLib:482, Marc Randolph
    • Re: ERROR:MapLib:482, Mich
      • Re: ERROR:MapLib:482, John McGrath
      • Re: ERROR:MapLib:482, Mich
      • Re: ERROR:MapLib:482, Mich
• VGA specification, me_2003
  • Re: VGA specification, Derek Simmons
  • Re: VGA specification, cs_posting
    • Re: VGA specification, Derek Simmons
      • Re: VGA specification, Jerry Coffin
  • Re: VGA specification, Jerry Coffin
    • Re: VGA specification, cs_posting
    • Re: VGA specification, Markus Kuhn
  • Re: VGA specification, jluisky
• Virtex 4 Multiplier RPM Constraints?, Love Singhal
  • Re: Virtex 4 Multiplier RPM Constraints?, Peter Alfke
    • Re: Virtex 4 Multiplier RPM Constraints?, Love Singhal
      • Re: Virtex 4 Multiplier RPM Constraints?, Peter Alfke
• about Xilinx Chipscope, yyqonline
  • Re: about Xilinx Chipscope, Mike Treseler
• FIFO design, siva007i
  • Re: FIFO design, Peter Alfke
• XC9500 JTAG Initialize problem, Chelam
  • Re: XC9500 JTAG Initialize problem, Antti
  • Re: XC9500 JTAG Initialize problem, Benjamin Todd
    • Re: XC9500 JTAG Initialize problem, :-)
• fpga to 5v ttl logic, aiiadict
  • Re: fpga to 5v ttl logic, cs_posting
  • Re: fpga to 5v ttl logic, Peter Alfke
    • Re: fpga to 5v ttl logic, Jim Granville
      • Re: fpga to 5v ttl logic, cs_posting
      • Re: fpga to 5v ttl logic, Jan Panteltje
      • Re: fpga to 5v ttl logic, Jim Granville
      • Re: fpga to 5v ttl logic, Peter Alfke
      • Re: fpga to 5v ttl logic, fpga_toys
      • Re: fpga to 5v ttl logic, Peter Alfke
      • Re: fpga to 5v ttl logic, langwadt
      • Re: fpga to 5v ttl logic, John_H
      • Re: fpga to 5v ttl logic, Jim Granville
    • Re: fpga to 5v ttl logic, Peter Wallace
  • communication b/w ethernet and fpga, aayush
• Low power consumption board with memory, Duccio
  • Re: Low power consumption board with memory, rickman
    • Re: Low power consumption board with memory, Hal Murray
  • Re: Low power consumption board with memory, John Adair
• VHDL to create LUT based delay, Brendan Illingworth
  • Re: VHDL to create LUT based delay, Alex
  • Re: VHDL to create LUT based delay, Peter Alfke
    • Re: VHDL to create LUT based delay, Thomas Reinemann
      • Re: VHDL to create LUT based delay, Peter Alfke
  • Re: VHDL to create LUT based delay, Amy
  • Re: VHDL to create LUT based delay, Jeremy Stringer
• Loop Optimization, Roberto
• A dev board supporting partial/dynamic reconf., pablo
  • Re: A dev board supporting partial/dynamic reconf., Stephen Craven
    • Re: A dev board supporting partial/dynamic reconf., pablo
      • Re: A dev board supporting partial/dynamic reconf., Antti Lukats
      • Re: A dev board supporting partial/dynamic reconf., Ivan
  • Re: A dev board supporting partial/dynamic reconf., Paul Hartke
  • Re: A dev board supporting partial/dynamic reconf., jenze
• V4 FIFO16 and SRAM, Brad Smallridge
  • Re: V4 FIFO16 and SRAM, Peter Alfke
    • Re: V4 FIFO16 and SRAM, Brad Smallridge
      • Re: V4 FIFO16 and SRAM, Sylvain Munaut
      • Re: V4 FIFO16 and SRAM, Brad Smallridge
      • Re: V4 FIFO16 and SRAM, Sylvain Munaut
      • Re: V4 FIFO16 and SRAM, Peter Alfke
      • Re: V4 FIFO16 and SRAM, Brad Smallridge
      • Re: V4 FIFO16 and SRAM, Peter Alfke
      • Re: V4 FIFO16 and SRAM, Hal Murray
      • Re: V4 FIFO16 and SRAM, Brad Smallridge
  • Re: V4 FIFO16 and SRAM, Ray Andraka
    • Re: V4 FIFO16 and SRAM, Peter Alfke
    • Re: V4 FIFO16 and SRAM, Brad Smallridge
      • Re: V4 FIFO16 and SRAM, Peter Alfke
      • Re: V4 FIFO16 and SRAM, Ray Andraka
      • Re: V4 FIFO16 and SRAM, Peter Alfke
      • Re: V4 FIFO16 and SRAM, Ray Andraka
• How about a "File Exchange" for System Generator designs?, Brady Gaughan
• Module-based partial reconfiguration in ISE Webpack, Fabio Rodrigues de la Rocha
  • Re: Module-based partial reconfiguration in ISE Webpack, rickman
  • Re: Module-based partial reconfiguration in ISE Webpack, Paul Hartke
• FPGA Selection Question, maxascent
  • Re: FPGA Selection Question, Austin Lesea
    • Re: FPGA Selection Question, Antti Lukats
      • Re: FPGA Selection Question, Austin Lesea
  • Re: FPGA Selection Question, Teo
  • Re: FPGA Selection Question, Luc
    • Re: FPGA Selection Question, maxascent
• Problem after P&R using Xilinx Viterbi Decoder IP, Arnaud
• [EDK] XilNet throughput, Johan Bernspång
  • Re: [EDK] XilNet throughput, Hal Murray
    • Re: [EDK] XilNet throughput, Johan Bernspång
• System Packet Interface?, freechip
  • Re: System Packet Interface?, Allan Herriman
• implement IP TCP Layer in FPGA, freechip
  • Re: implement IP TCP Layer in FPGA, Phil Hays
  • Re: implement IP TCP Layer in FPGA, Hans
• a master-IPIF problem on the PLB bus, Mich
• The 95108 cpld is getting heated when connected by CRO, Augast15
  • Re: The 95108 cpld is getting heated when connected by CRO, Andy Peters
  • Re: The 95108 cpld is getting heated when connected by CRO, Leon
  • Re: The 95108 cpld is getting heated when connected by CRO, Klaus Falser
    • Re: The 95108 cpld is getting heated when connected by CRO, Augast15
      • Re: The 95108 cpld is getting heated when connected by CRO, Leon
      • Re: The 95108 cpld is getting heated when connected by CRO, Jim Granville
      • Re: The 95108 cpld is getting heated when connected by CRO, Benjamin Todd
      • Re: The 95108 cpld is getting heated when connected by CRO, Leon
• PPC405 - FPGA interface design, amit
  • Re: PPC405 - FPGA interface design, Antti
• Need a SPI 4?, freechip
  • Re: Need a SPI 4?, Allan Herriman
• USB 2.0 OTG in FPGA, Martin Bosma
  • Re: USB 2.0 OTG in FPGA, Antti
    • Re: USB 2.0 OTG in FPGA, Martin Bosma
      • Re: USB 2.0 OTG in FPGA, Uwe Bonnes
      • Re: USB 2.0 OTG in FPGA, Antti
      • Re: USB 2.0 OTG in FPGA, Antti
• configuring Hardware, ABS
  • Re: configuring Hardware, backhus
    • Re: configuring Hardware, ABS
• ironic Xcell journal 1Q2006 cover art, S3E Starter Kit, Eric Smith
  • Re: ironic Xcell journal 1Q2006 cover art, S3E Starter Kit, John_H
    • Re: ironic Xcell journal 1Q2006 cover art, S3E Starter Kit, Brian Davis
      • Re: ironic Xcell journal 1Q2006 cover art, S3E Starter Kit, Jerry Coffin
      • Re: ironic Xcell journal 1Q2006 cover art, S3E Starter Kit, Jerry Coffin
      • Re: ironic Xcell journal 1Q2006 cover art, S3E Starter Kit, Brian Davis
      • Re: ironic Xcell journal 1Q2006 cover art, S3E Starter Kit, Jerry Coffin
      • Re: ironic Xcell journal 1Q2006 cover art, S3E Starter Kit, Brian Davis
      • Re: ironic Xcell journal 1Q2006 cover art, S3E Starter Kit, Brian Davis
  • Re: ironic Xcell journal 1Q2006 cover art, S3E Starter Kit, Antti
  • Re: ironic Xcell journal 1Q2006 cover art, S3E Starter Kit, John Adair
    • Re: ironic Xcell journal 1Q2006 cover art, S3E Starter Kit, Antti
      • Re: ironic Xcell journal 1Q2006 cover art, S3E Starter Kit, John Adair
• Re: Analog FPGA Project -- VIdeo Router, Robert Finch
• Raggedstone1 - New Worldwide postage, John Adair
• Variables in VHDL and simulation, Fabio Rodrigues de la Rocha
  • Re: Variables in VHDL and simulation, Mike Treseler
  • Re: Variables in VHDL and simulation, Brian Drummond
• using evaluated ip core with edk 7.1 i, chhavi
• How to use a .coe file for rom/ram in system generator, Glenn
• From ASM to verilog Code, prasunp
• 8051 IP core with JTAG debugger for FPGA?, Pszemol
  • Re: 8051 IP core with JTAG debugger for FPGA?, Antti Lukats
    • Re: 8051 IP core with JTAG debugger for FPGA?, Robert F. Jarnot
      • Re: 8051 IP core with JTAG debugger for FPGA?, Pszemol
      • Re: 8051 IP core with JTAG debugger for FPGA?, Robert F. Jarnot
      • Re: 8051 IP core with JTAG debugger for FPGA?, Hal Murray
      • Re: 8051 IP core with JTAG debugger for FPGA?, Hans
      • Re: 8051 IP core with JTAG debugger for FPGA?, Jim Granville
    • Re: 8051 IP core with JTAG debugger for FPGA?, Pszemol
  • Re: 8051 IP core with JTAG debugger for FPGA?, Steve Knapp (Xilinx Spartan-3 Generation FPGAs)
• Spartan3 decoupling, Marco
• High Speed Development Board, freechip
  • Re: High Speed Development Board, freechip
• need byteblaster II source code, chudar
  • Re: need byteblaster II source code, Noway2
• Re: EDK 7.1 XMD and platform USB cable, pejdstran
• project validation: best procedures?, Emanuel Machado
  • Re: project validation: best procedures?, Mike Treseler
  • Re: project validation: best procedures?, Hans
• altera max 7128s blanking, djanisz
  • Re: altera max 7128s blanking, Noway2
    • Re: altera max 7128s blanking, djanisz
      • Re: altera max 7128s blanking, Noway2
• System with multiple buses, Marco T.
• ARCnet interface gate count, Nicolas Matringe
  • Re: ARCnet interface gate count, Allan Herriman
    • Re: ARCnet interface gate count, Nicolas Matringe
• DDR2 Memory Design: Layout, timing, swimmer_
  • Re: DDR2 Memory Design: Layout, timing, Antti
  • Re: DDR2 Memory Design: Layout, timing, PeteS
    • Re: DDR2 Memory Design: Layout, timing, swimmer_
      • Re: DDR2 Memory Design: Layout, timing, PeteS
      • Re: DDR2 Memory Design: Layout, timing, PeteS
• virtex 4, Ernest Scheiber
  • Re: virtex 4, Antti
    • Re: virtex 4, John Adair
• Combinatorial Division?, logjam
  • Re: Combinatorial Division?, Eric Smith
    • Re: Combinatorial Division?, Robert Finch
      • Re: Combinatorial Division?, logjam
      • Re: Combinatorial Division?, Isaac Bosompem
      • Re: Combinatorial Division?, logjam
      • Re: Combinatorial Division?, Isaac Bosompem
      • Re: Combinatorial Division?, Michael Hennebry
  • Re: Combinatorial Division?, Peter Alfke
    • Re: Combinatorial Division?, logjam
      • Re: Combinatorial Division?, Jeff Cunningham
      • Re: Combinatorial Division?, Isaac Bosompem
      • Re: Combinatorial Division?, logjam
      • Re: Combinatorial Division?, logjam
      • Re: Combinatorial Division?, fpga_toys
      • Re: Combinatorial Division?, Peter Alfke
      • Re: Combinatorial Division?, logjam
      • Re: Combinatorial Division?, Peter Alfke
      • Re: Combinatorial Division?, Eric Smith
      • Re: Combinatorial Division?, fpga_toys
      • Re: Combinatorial Division?, Falk Brunner
      • Re: Combinatorial Division?, Isaac Bosompem
      • Re: Combinatorial Division?, Jan Panteltje
      • Re: Combinatorial Division?, Isaac Bosompem
      • Re: Combinatorial Division?, Jan Panteltje
    • Re: Combinatorial Division?, Jan Panteltje
    • Re: Combinatorial Division?, David R Brooks
      • Re: Combinatorial Division?, fpga_toys
  • Re: Combinatorial Division?, Josh Rosen
    • Re: Combinatorial Division?, fpga_toys
      • Re: Combinatorial Division?, Josh Rosen
      • Re: Combinatorial Division?, fpga_toys
      • Re: Combinatorial Division?, Josh Rosen
      • Re: Combinatorial Division?, fpga_toys
      • Re: Combinatorial Division?, Peter Alfke
      • Re: Combinatorial Division?, fpga_toys
      • Re: Combinatorial Division?, Peter Alfke
      • Re: Combinatorial Division?, Michael Hennebry
      • Re: Combinatorial Division?, Philip Freidin
      • Re: Combinatorial Division?, Isaac Bosompem
  • Re: Combinatorial Division?, Derek Simmons
    • Re: Combinatorial Division?, logjam
      • Re: Combinatorial Division?, Jan Panteltje
      • Re: Combinatorial Division?, Jan Panteltje
• OpenRisc 1200 on Spartan 3 - problems with stability and enabling cache, Thomas Oehme
  • Re: OpenRisc 1200 on Spartan 3 - problems with stability and enabling cache, Aurelian Lazarut
    • Re: OpenRisc 1200 on Spartan 3 - problems with stability and enabling cache, Thomas Oehme
      • Re: OpenRisc 1200 on Spartan 3 - problems with stability and enabling cache, Aurelian Lazarut
  • Re: OpenRisc 1200 on Spartan 3 - problems with stability and enabling cache, Javier Castillo
• Truth about Spartan-3E DCM speed, Finn S. Nielsen
  • Re: Truth about Spartan-3E DCM speed, Austin Lesea
    • Re: Truth about Spartan-3E DCM speed, Finn S. Nielsen
• Kalman filters, mnemo5
  • Re: Kalman filters, TC
    • Re: Kalman filters, mk
      • Re: Kalman filters, TC
      • Re: Kalman filters, mnemo5
      • Re: Kalman filters, backhus
      • Re: Kalman filters, mnemo5
      • Re: Kalman filters, TC
• query!! need help!!, pavan
  • Re: query!! need help!!, Michael Schöberl
  • Re: query!! need help!!, David R Brooks
• Checkpointing PPC Smartmodels in ModelSim 6.0b Issues, Nju Njoroge
  • Re: Checkpointing PPC Smartmodels in ModelSim 6.0b Issues, Hans
  • Re: Checkpointing PPC Smartmodels in ModelSim 6.0b Issues, Brian Drummond
    • Re: Checkpointing PPC Smartmodels in ModelSim 6.0b Issues, Brian Drummond
• JTAG problem, mughat
  • Re: JTAG problem, Neil Glenn Jacobson
  • Re: JTAG problem, John Adair
    • Re: JTAG problem, mughat
      • Re: JTAG problem, Neil Glenn Jacobson
• FPGA to ASIC migrate, Jerzy Gbur
  • Re: FPGA to ASIC migrate, Austin Lesea
    • Re: FPGA to ASIC migrate, Gabor
    • Re: FPGA to ASIC migrate, Jerzy Gbur
      • Re: FPGA to ASIC migrate, Gabor
• Ray Andraka's Book?, Stephen Craven
  • Re: Ray Andraka's Book?, Ray Andraka
• state machine and i2c, embyembu
  • Re: state machine and i2c, Alan Myler
• PowerPC based SoC design, getting it working from first attempt, Antti
  • Re: PowerPC based SoC design, getting it working from first attempt, Ivan
    • Re: PowerPC based SoC design, getting it working from first attempt, Antti
      • Re: PowerPC based SoC design, getting it working from first attempt, Ivan
• configuring stratix GX Fpga, pinku
  • Re: configuring stratix GX Fpga, venkatec
• RC1000pp with XCV400, Colin F
• Virtex-4 Output Primitive, Brad Smallridge
• Re: Virtex-4 ISERDES and ADS527X ADCs, Brian Davis
• Cannot use ML310 DDR, king_azman
  • Re: Cannot use ML310 DDR, beeraka@xxxxxxxxx
    • Re: Cannot use ML310 DDR, Stephen Craven
      • Re: Cannot use ML310 DDR, king_azman
• Layer 2 (MAC) Research Project to Eliminate Routers, Perfect Queue
  • Re: Layer 2 (MAC) Research Project to Eliminate Routers, Simon Peacock
• Re: Xilinx ISE 6.3 confusion with CPLD logic results, Wouter Coene
• How to make Customized IP which connected with Microblaze through FSL access the OPB bus?, fpga
  • Re: How to make Customized IP which connected with Microblaze through FSL access the OPB bus?, Antti
    • Re: How to make Customized IP which connected with Microblaze through FSL access the OPB bus?, fpga
      • Re: How to make Customized IP which connected with Microblaze through FSL access the OPB bus?, Antti
      • Re: How to make Customized IP which connected with Microblaze through FSL access the OPB bus?, fpga
      • Re: How to make Customized IP which connected with Microblaze through FSL access the OPB bus?, fpga
      • Re: How to make Customized IP which connected with Microblaze through FSL access the OPB bus?, fpga
      • Re: How to make Customized IP which connected with Microblaze through FSL access the OPB bus?, Ivan
      • Re: How to make Customized IP which connected with Microblaze through FSL access the OPB bus?, fpga
      • Re: How to make Customized IP which connected with Microblaze through FSL access the OPB bus?, Ivan
      • Re: How to make Customized IP which connected with Microblaze through FSL access the OPB bus?, fpga
  • Re: How to make Customized IP which connected with Microblaze through FSL access the OPB bus?, Antti
    • Re: How to make Customized IP which connected with Microblaze through FSL access the OPB bus?, Ivan
• bypass between ilogic and ologic, Brannon
  • Re: bypass between ilogic and ologic, Eric Crabill
• Relative placement constraints in Xilinx ISE w/ Verilog, nestorj@xxxxxxxxxxxxx
  • Re: Relative placement constraints in Xilinx ISE w/ Verilog, Ray Andraka
• Virtex2: can I really just leave M1,M2,M3 pins floating?, ML
  • Re: Virtex2: can I really just leave M1,M2,M3 pins floating?, mike_la_jolla
• fix: Xilinx USB Platform Cable on linux 2.6, Stefan
  • Re: fix: Xilinx USB Platform Cable on linux 2.6, Stefan
    • Re: fix: Xilinx USB Platform Cable on linux 2.6, Stefan
• How to use Gigabit transciever, pinku
  • Re: How to use Gigabit transciever, gregs
• EDK 8.1 SP1 released, DDR2 support is now included !!, Antti
• DSP, SaHiD
  • Re: DSP, Philip Freidin
• SMSC 91c111 and LwIP, Marco T.
  • Re: SMSC 91c111 and LwIP, Dominik Froehlich
    • Re: SMSC 91c111 and LwIP, Marco T.
• Xilinx Spartan 3 SSO guidelines for CP132 package?, Andrew FPGA
  • Re: Xilinx Spartan 3 SSO guidelines for CP132 package?, Andrew FPGA
• "par.exe" halted without error (partial configuratio), Pasacco
  • Re: "par.exe" halted without error (partial configuratio), Brannon
    • Re: "par.exe" halted without error (partial configuratio), John Williams
• FPGA work - San Diego area, great_headhunter
• arctangent again, mk
  • Re: arctangent again, great_headhunter
  • Re: arctangent again, Marko
• EDK -running from external sram, me_2003
  • Re: EDK -running from external sram, Aurelian Lazarut
• Any one worked with Digilent Adept(transport) feature??, k.sandeep.p
• SDRAM Reading problem, raju_lingala
• Xilinx 8.1.02i map failure, johnp
  • Re: Xilinx 8.1.02i map failure, johnp
    • Re: Xilinx 8.1.02i map failure, Simon Peacock
• Is FPGA code called firmware?, Marko
  • Re: Is FPGA code called firmware?, Falk Brunner
    • Re: Is FPGA code called firmware?, Marko
      • Re: Is FPGA code called firmware?, Falk Brunner
      • Re: Is FPGA code called firmware?, Bob Perlman
    • Re: Is FPGA code called firmware?, Julian Kain
      • Re: Is FPGA code called firmware?, Falk Brunner
      • Re: Is FPGA code called firmware?, mk
      • Re: Is FPGA code called firmware?, Falk Brunner
      • Re: Is FPGA code called firmware?, fpga_toys
      • Re: Is FPGA code called firmware?, Falk Brunner
      • Re: Is FPGA code called firmware?, fpga_toys
  • Re: Is FPGA code called firmware?, Tim Wescott
  • Re: Is FPGA code called firmware?, soar2morrow
    • Re: Is FPGA code called firmware?, fpga_toys
    • Re: Is FPGA code called firmware?, Ray Andraka
  • Re: Is FPGA code called firmware?, James Morrison
  • Re: Is FPGA code called firmware?, Joseph Samson
  • Re: Is FPGA code called firmware?, reiner
    • Re: Is FPGA code called firmware?, Falk Brunner
    • Re: Is FPGA code called firmware?, Kolja Sulimma
      • Re: Is FPGA code called firmware?, Stephane
  • Re: Is FPGA code called firmware?, Joseph Samson
    • Re: Is FPGA code called firmware?, Brannon
    • Re: Is FPGA code called firmware?, JJ
    • Re: Is FPGA code called firmware?, JJ
  • Re: Is FPGA code called firmware?, Brannon
    • Re: Is FPGA code called gateware?, Mike Treseler
      • Re: Is FPGA code called gateware?, Bob Perlman
      • Re: Is FPGA code called gateware?, Tim Wescott
      • Re: Is FPGA code called gateware?, Isaac Bosompem
      • Re: Is FPGA code called gateware?, fpga_toys
      • Re: Is FPGA code called gateware?, Gabor
      • Re: Is FPGA code called gateware?, fpga_toys
      • Re: Is FPGA code called gateware?, Jim Granville
      • Re: Is FPGA code called gateware?, fpga_toys
      • Re: Is FPGA code called gateware?, mk
      • Re: Is FPGA code called gateware?, fpga_toys
      • Re: Is FPGA code called gateware?, Jim Granville
      • Re: Is FPGA code called gateware?, fpga_toys
      • Re: Is FPGA code called gateware?, Andy Peters
      • Re: Is FPGA code called gateware?, Mike Treseler
      • Re: Is FPGA code called gateware?, Isaac Bosompem
      • Re: Is FPGA code called gateware?, Isaac Bosompem
      • Re: Is FPGA code called gateware?, fpga_toys
      • Re: Is FPGA code called gateware?, Hal Murray
      • Re: Is FPGA code called gateware?, fpga_toys
      • Re: Is FPGA code called gateware?, Nial Stewart
      • Re: Is FPGA code called gateware?, fpga_toys
      • Re: Is FPGA code called gateware?, JJ
      • Re: Is FPGA code called gateware?, Nial Stewart
      • Re: Is FPGA code called gateware?, fpga_toys
      • Re: Is FPGA code called gateware?, Nial Stewart
      • Re: Is FPGA code called gateware?, fpga_toys
      • Re: Is FPGA code called gateware?, Colin Paul Gloster
      • Re: Is FPGA code called gateware?, JJ
      • Re: Is FPGA code called gateware?, fpga_toys
      • Re: Is FPGA code called gateware?, Mike Treseler
    • Re: Is FPGA code called firmware?, Tim Wescott
  • Re: Is FPGA code called firmware?, ghelbig
• Quartus Tcl interface, ernie
  • Re: Quartus Tcl interface, ernie
• Inactive signals are active!!! - Chipscope Pro 7.1i - SP4, simon.stockton@xxxxxxxxxxxxxx
  • Re: Inactive signals are active!!! - Chipscope Pro 7.1i - SP4, Michael Schöberl
    • Re: Inactive signals are active!!! - Chipscope Pro 7.1i - SP4, simon.stockton@xxxxxxxxxxxxxx
      • Re: Inactive signals are active!!! - Chipscope Pro 7.1i - SP4, simon.stockton@xxxxxxxxxxxxxx
• PPC LUT inputs/outputs, munch
• DVI - LVDS controller, helix
  • Re: DVI - LVDS controller, Antti
    • Re: DVI - LVDS controller, helix
      • Re: DVI - LVDS controller, Antti
• multiphase data extraction question, Sandro
  • Re: multiphase data extraction question, Philip Freidin
    • Re: multiphase data extraction question, Sandro
      • Re: multiphase data extraction question, Andy
      • Re: multiphase data extraction question, Symon
    • Re: multiphase data extraction question, Symon
      • Re: multiphase data extraction question, Sandro
• Problem with multple clcok domains, Sunny
  • Re: Problem with multple clcok domains, Hendra
  • Re: Problem with multple clcok domains, Sylvain Munaut <SomeOne@xxxxxxxxxxxxxx>
  • Re: Problem with multple clcok domains, mk
• Parameterized Comparator Verilog Code, prasunp
  • Re: Parameterized Comparator Verilog Code, John_H
• Inferring Adder with Carry In and Cary out, Sudhir . Singh
• FPGA - software or hardware?, Hub van de Bergh
  • Re: FPGA - software or hardware?, Rich Webb
    • Re: FPGA - software or hardware?, Hans
  • Re: FPGA - software or hardware?, Bob Perlman
    • Re: FPGA - software or hardware?, JJ
  • Re: FPGA - software or hardware?, Phil Hays
    • Re: FPGA - software or hardware?, Philip Freidin
      • Re: FPGA - software or hardware?, Isaac Bosompem
      • Re: FPGA - software or hardware?, JJ
      • Re: FPGA - software or hardware?, Jerry Coffin
      • Message not available
      • Cheating at homework (from "Re: FPGA - software or hardware?"), Colin Paul Gloster
      • Re: Cheating at homework (from "Re: FPGA - software or hardware?"), Falk Brunner
      • Re: Cheating at homework (from "Re: FPGA - software or hardware?"), Symon
      • Re: Cheating at homework (from "Re: FPGA - software or hardware?"), Anonymous
      • Re: Cheating at homework (from "Re: FPGA - software or hardware?"t, JJ
      • Re: Cheating at homework (from "Re: FPGA - software or hardware?"t, Chris Gammell
      • Re: FPGA - software or hardware?, Falk Brunner
      • Re: FPGA - software or hardware?, kcl
  • Re: FPGA - software or hardware?, Pleae_do_my_homework
  • Re: FPGA - software or hardware?, Thomas Stanka
  • FPGA - software or hardware -2-, Hub van de Bergh
    • Re: FPGA - software or hardware -2-, fpga_toys
    • Re: FPGA - software or hardware -2-, Hal Murray
      • Re: FPGA - software or hardware -2-, se
    • Re: FPGA - software or hardware -2-, Peter Alfke
      • Re: FPGA - software or hardware -2-, Simon Peacock
      • Re: FPGA - software or hardware -2-, fpga_toys
      • Re: FPGA - software or hardware -2-, Hal Murray
      • Re: FPGA - software or hardware -2-, Jeremy Stringer
      • Re: FPGA - software or hardware -2-, fpga_toys
      • Re: FPGA - software or hardware -2-, Ben Jones
      • [OT] FPGA - software or hardware -2-, Symon
      • Re: FPGA - software or hardware -2-, Simon Peacock
      • Re: FPGA - software or hardware -2-, Hal Murray
      • Re: FPGA - software or hardware -2-, Simon Peacock
      • Re: FPGA - software or hardware -2-, Eric Smith
      • Re: FPGA - software or hardware -2-, Eric Smith
      • Re: FPGA - software or hardware -2-, Brian Drummond
      • Re: FPGA - software or hardware -2-, Hal Murray
    • Re: FPGA - software or hardware -2-, Jim Granville
      • Re: FPGA - software or hardware -2-, fpga_toys
      • Re: FPGA - software or hardware -2-, JJ
      • Re: FPGA - software or hardware -2-, fpga_toys
• FPGA Board Competition, John Adair
• help with VGA timings, Jordi
  • Re: help with VGA timings, Sylvain Munaut
  • Re: help with VGA timings, Paul Hartke
  • Re: help with VGA timings, Jan Panteltje
    • Re: help with VGA timings, Mike Harrison
      • Re: help with VGA timings, Sylvain Munaut
      • Re: help with VGA timings, Isaac Bosompem
      • Re: help with VGA timings, Jordi
      • Re: help with VGA timings, Isaac Bosompem
      • Re: help with VGA timings, Jan Panteltje
      • Re: help with VGA timings, Gabor
• Addressing BRAM in a V2 pro, Mich
  • Re: Addressing BRAM in a V2 pro, Isaac Bosompem
    • Re: Addressing BRAM in a V2 pro, Peter Alfke
  • Re: Addressing BRAM in a V2 pro, Johan Bernspång
    • Re: Addressing BRAM in a V2 pro, Mich
      • Re: Addressing BRAM in a V2 pro, Antti
      • Re: Addressing BRAM in a V2 pro, Mich
• FPT'06: First Call-for-paper, Yod
• Did anyone doing research on power electronics control using FPGA?, kk
• What is the best price you have gotten on for these FPGAs?, rickman
  • Re: What is the best price you have gotten on for these FPGAs?, Simon Peacock
  • Re: What is the best price you have gotten on for these FPGAs?, Uwe Bonnes
    • Re: What is the best price you have gotten on for these FPGAs?, rickman
  • Re: What is the best price you have gotten on for these FPGAs?, John Adair
    • Re: What is the best price you have gotten on for these FPGAs?, rickman
      • Re: What is the best price you have gotten on for these FPGAs?, Antti
• MontaVista Linux and Virtex-II & 4, Osnet
  • Re: MontaVista Linux and Virtex-II & 4, Paul Hartke
    • Re: MontaVista Linux and Virtex-II & 4, Sylvain Munaut
      • Re: MontaVista Linux and Virtex-II & 4, Rainer Buchty
      • Re: MontaVista Linux and Virtex-II & 4, Sylvain Munaut
      • Re: MontaVista Linux and Virtex-II & 4, Rainer Buchty
• Xilinx ISE Simulator Arrays, Brad Smallridge
  • Re: Xilinx ISE Simulator Arrays, Hendra
• Approximate power and area values for a 1-bit SRAM cell., vivekgarg330
• PC104+ Card, John Adair
• Xilinx System Generator Black Box, cwoodring
• Xilinx HardMacro "configurable" ?, Sylvain Munaut
  • Re: Xilinx HardMacro "configurable" ?, Antti Lukats
    • Re: Xilinx HardMacro "configurable" ?, Sylvain Munaut
      • Re: Xilinx HardMacro "configurable" ?, Antti Lukats
      • Re: Xilinx HardMacro "configurable" ?, Sylvain Munaut
      • Re: Xilinx HardMacro "configurable" ?, Antti Lukats
      • Re: Xilinx HardMacro "configurable" ?, Sylvain Munaut
      • Re: Xilinx HardMacro "configurable" ?, Stephane
      • Re: Xilinx HardMacro "configurable" ?, Allan Herriman
• using ISE and GNU tools for Xilinx V2Pro/V4FX PowerPC, Antti Lukats
• Xilinx development board, vssumesh
  • Re: Xilinx development board, John Adair
    • Re: Xilinx development board, vssumesh
      • Re: Xilinx development board, John Adair
  • <Possible follow-ups>
  • Xilinx development board, vssumesh
• Find and fix critical paths in gate level netlist by GOF, nandigits
• ISE Simulator Price, Hendra
  • Re: ISE Simulator Price, Antti Lukats
  • Re: ISE Simulator Price, Paul Hartke
  • Re: ISE Simulator Price, Steve Lass
    • Re: ISE Simulator Price, Eric Smith
      • Re: ISE Simulator Price, Simon Peacock
• open position: developing high-level FPGA programming tools, Fergus Henderson
• low level ethernet interface driver, Steve Perrin
• equivalent time sampling, maxascent
  • Re: equivalent time sampling, John_H
    • Re: equivalent time sampling, maxascent
      • Re: equivalent time sampling, Allan Herriman
      • Re: equivalent time sampling, John_H
      • Re: equivalent time sampling, maxascent
      • Re: equivalent time sampling, John_H
      • Re: equivalent time sampling, Philip Freidin
      • Re: equivalent time sampling, John_H
      • Re: equivalent time sampling, maxascent
• Xilinx UCF area constraints disappearing, Roger
  • Re: Xilinx UCF area constraints disappearing, MM
    • Re: Xilinx UCF area constraints disappearing, Brian Drummond
  • Re: Xilinx UCF area constraints disappearing, cwoodring
  • Re: Xilinx UCF area constraints disappearing, Roger
• Memory initialization for synthesis in ISE, Sleep Mode
• Poll: what's would your requirments be for ESL (Electronic System Level) flows?, Alfredo
  • Re: what's would your requirments be for ESL (Electronic System Level) flows?, Symon
  • Re: what's would your requirments be for ESL (Electronic System Level) flows?, John_H
    • Re: what's would your requirments be for ESL (Electronic System Level) flows?, Alfredo
• Communication between FPGA and PC with ethernet, Roggey
  • Re: Communication between FPGA and PC with ethernet, Noway2
    • Communication between FPGA and PC with ethernet card, aayush
      • Re: Communication between FPGA and PC with ethernet card, mk
  • Re: Communication between FPGA and PC with ethernet, Markus Kuhn
  • Re: Communication between FPGA and PC with ethernet, GHEDWHCVEAIS@xxxxxxxxxxxxx
    • Re: Communication between FPGA and PC with ethernet, Mike Harrison
      • Re: Communication between FPGA and PC with ethernet, Roggey
    • Re: Communication between FPGA and PC with ethernet, mk
    • Re: Communication between FPGA and PC with ethernet, hansp
      • Re: Communication between FPGA and PC with ethernet, cs_posting
    • Re: Communication between FPGA and PC with ethernet, Roggey
  • Re: Communication between FPGA and PC with ethernet, Hal Murray
• Xilinx Tight packing : Map error, the tools don't get it ..., Sylvain Munaut
  • Re: Xilinx Tight packing : Map error, the tools don't get it ..., Symon
    • Re: Xilinx Tight packing : Map error, the tools don't get it ..., Sylvain Munaut
  • Re: Xilinx Tight packing : Map error, the tools don't get it ..., John_H
    • Re: Xilinx Tight packing : Map error, the tools don't get it ..., Sylvain Munaut
      • Re: Xilinx Tight packing : Map error, the tools don't get it ..., JustJohn
      • Re: Xilinx Tight packing : Map error, the tools don't get it ..., Sylvain Munaut
• Standby current measurement, Roger Bourne
• sdram modeling, Andy Luotto
• [Handel-C]Interface with C, Rob
  • <Possible follow-ups>
  • [Handel-C]Interface with C, Roberto
• VHDL simulation, logjam
  • Re: VHDL simulation, Shyam
    • Re: VHDL simulation, logjam
• Maxim anounce MAX3421E SPI-USB Host/Peri, Jim Granville
  • Re: Maxim anounce MAX3421E SPI-USB Host/Peri, Sylvain Munaut
    • Re: Maxim anounce MAX3421E SPI-USB Host/Peri, Mike Harrison
      • Re: Maxim anounce MAX3421E SPI-USB Host/Peri, Uwe Bonnes
• opencores.org ?, pbdelete
  • Re: opencores.org ?, GHEDWHCVEAIS@xxxxxxxxxxxxx
  • Re: opencores.org ?, Luc
    • Re: opencores.org ?, v_mirgorodsky
• Xilinx EDK GPIO: Can I drive internal logic with it?, MM
  • Re: Xilinx EDK GPIO: Can I drive internal logic with it?, Joseph Samson
    • Re: Xilinx EDK GPIO: Can I drive internal logic with it?, MM
• WIFI Compact Flash, eziggurat
  • Re: WIFI Compact Flash, Mike Harrison
  • Re: WIFI Compact Flash, Isaac Bosompem
• Need some Advice, please, benkhalh
  • Re: Need some Advice, please, Peter Alfke
    • Re: Need some Advice, please, benkhalh
      • Re: Need some Advice, please, Peter Alfke
  • Re: Need some Advice, please, Tim Wescott
    • Re: Need some Advice, please, benkhalh
  • Re: Need some Advice, please, Isaac Bosompem
    • Re: Need some Advice, please, benkhalh
• User masks in HardCopy and HardCopy II, Shyam
  • Re: User masks in HardCopy and HardCopy II, Paul Hollingworth
    • Re: User masks in HardCopy and HardCopy II, Jim Granville
    • Re: User masks in HardCopy and HardCopy II, Shyam
• Implementing a two-modulus PLL divider in Altera Stratix II, Markus Kuhn
  • Re: Implementing a two-modulus PLL divider in Altera Stratix II, Peter Alfke
    • Re: Implementing a two-modulus PLL divider in Altera Stratix II, austin
  • Re: Implementing a two-modulus PLL divider in Altera Stratix II, Hal Murray
    • Re: Implementing a two-modulus PLL divider in Altera Stratix II, Allan Herriman
    • Re: Implementing a two-modulus PLL divider in Altera Stratix II, John_H
• VHDL or verilog, CMOS
  • Re: VHDL or verilog, Dominik Froehlich
  • Re: VHDL or verilog, Joseph Samson
  • Re: VHDL or verilog, Mike Harrison
    • Re: VHDL or verilog, Andy Peters
  • Re: VHDL or verilog, Josh Rosen
    • Re: VHDL or verilog, Dominik Froehlich
  • Re: VHDL or verilog, eziggurat
    • Re: VHDL or verilog, CMOS
• DDR SDRAM Controller, ada
  • Re: DDR SDRAM Controller, Gabor
    • Re: DDR SDRAM Controller, ada
      • Re: DDR SDRAM Controller, Gabor
      • Re: DDR SDRAM Controller, ALuPin@xxxxxx
      • Re: DDR SDRAM Controller, ada
      • Re: DDR SDRAM Controller, Sylvain Munaut
      • Re: DDR SDRAM Controller, boh!
  • Re: DDR SDRAM Controller, Michael Schöberl
    • Re: DDR SDRAM Controller, Sylvain Munaut <SomeOne@xxxxxxxxxxxxxx>
      • Re: DDR SDRAM Controller, ada
      • Re: DDR SDRAM Controller, Falk Brunner
      • Re: DDR SDRAM Controller, ALuPin@xxxxxx
      • Re: DDR SDRAM Controller, ada
      • Re: DDR SDRAM Controller, ALuPin@xxxxxx
      • Re: DDR SDRAM Controller, PeteS
      • Re: DDR SDRAM Controller, ada
      • Re: DDR SDRAM Controller, PeteS
      • Re: DDR SDRAM Controller, Gabor
  • <Possible follow-ups>
  • DDR SDRAM Controller, Brendan Illingworth
  • DDR SDRAM Controller, Brendan Illingworth
    • Re: DDR SDRAM Controller, PeteS
      • Re: DDR SDRAM Controller, Brendan Illingworth
      • Re: DDR SDRAM Controller, PeteS
• pci express ac coupling, colin
  • Re: pci express ac coupling, Gabor
    • Re: pci express ac coupling, Ian Muncaster
• delay using integrator, Sonali
  • Re: delay using integrator, Gabor
• EDl Lab, John Adair
• WebPACK license (and Quartus Web Edition too)., zlyh
  • Re: WebPACK license (and Quartus Web Edition too)., Alan Myler
    • Re: WebPACK license (and Quartus Web Edition too)., Karl
    • Re: WebPACK license (and Quartus Web Edition too)., zlyh
    • Message not available
      • Re: WebPACK license (and Quartus Web Edition too)., fpga_toys
  • Re: WebPACK license (and Quartus Web Edition too)., Alex K
    • Re: WebPACK license (and Quartus Web Edition too)., Ed McGettigan
  • Re: WebPACK license (and Quartus Web Edition too)., Steve Lass
• CPLD-SPI_flash configuration system problem., mughat
  • Re: CPLD-SPI_flash configuration system problem., Gabor
    • Re: CPLD-SPI_flash configuration system problem., mughat
      • Re: CPLD-SPI_flash configuration system problem., Gabor
• What is 1QN and 2QN in Xilinx CORDIC ?, ML
  • Re: What is 1QN and 2QN in Xilinx CORDIC ?, Ray Andraka
• DIFF_OUT buffer example, Brian Davis
  • Re: DIFF_OUT buffer example, Symon
    • Re: DIFF_OUT buffer example, Brian Davis
      • Re: DIFF_OUT buffer example, Symon
      • Re: DIFF_OUT buffer example, Hal Murray
      • Re: DIFF_OUT buffer example, Brian Davis
    • Re: DIFF_OUT buffer example, Tim
      • Re: DIFF_OUT buffer example, Symon
      • Re: DIFF_OUT buffer example, Brian Davis
  • Re: DIFF_OUT buffer example, Andy
    • Re: DIFF_OUT buffer example, Brian Davis
    • Re: DIFF_OUT buffer example, Sandro
• system generator : interrupt with FSL, upforever
• Altera Stratix EP1S80 DSP Development Board Non-Volatile Configuration, Louis Dupont
• EDK Woes and Worries, Chris Gammell
  • Re: EDK Woes and Worries, Antti
  • Re: EDK Woes and Worries, MM
    • Re: EDK Woes and Worries, Chris Gammell
      • Re: EDK Woes and Worries, MM
      • Re: EDK Woes and Worries, Peter Alfke
      • Re: EDK Woes and Worries, Chris Gammell
    • Re: EDK Woes and Worries, Symon
• DDR SDRAM on ML401, al99999
• News from Embedded World in Nurnber, Antti
  • Re: News from Embedded World in Nurnber, Falk Brunner
    • Re: News from Embedded World in Nurnber, Antti
      • Re: News from Embedded World in Nurnber, David Brown
      • Re: News from Embedded World in Nurnber, Falk Brunner
  • Re: News from Embedded World in Nurnber, Uwe Bonnes
  • Re: News from Embedded World in Nurnber, Antti Lukats
    • Re: News from Embedded World in Nurnber, Teo
    • Re: News from Embedded World in Nurnber, Jim Granville
• can i use gcc of EDK?, ramesh
  • Re: can i use gcc of EDK?, Sylvain Munaut <SomeOne@xxxxxxxxxxxxxx>
• Re: What is back_annotate?, Alan Myler
  • Re: What is back_annotate?, v_mirgorodsky
  • <Possible follow-ups>
  • Re: What is back_annotate?, Subroto Datta
• Re: Problem of Initial Value in VHDL code, agi
• Xilinx EDK BRAM confusion, MM
  • Re: Xilinx EDK BRAM confusion, Paulo Dutra
    • Re: Xilinx EDK BRAM confusion, Paulo Dutra
    • Re: Xilinx EDK BRAM confusion, MM
      • Re: Xilinx EDK BRAM confusion, Paulo Dutra
• EDK: OPB Question, me_2003
  • Re: EDK: OPB Question, Paulo Dutra
• Xilinx HDLParsers:810 or HDLParsers:3329, mattdykes
  • Message not available
    • Re: Xilinx HDLParsers:810 or HDLParsers:3329, mattdykes
      • Re: Xilinx HDLParsers:810 or HDLParsers:3329, Symon
• dynamic partial reconfiguration of Xilinx Virtex-4 FPGAs, zhangxun0501
  • Re: dynamic partial reconfiguration of Xilinx Virtex-4 FPGAs, Symon
    • Re: dynamic partial reconfiguration of Xilinx Virtex-4 FPGAs, Steve Lass
  • Re: dynamic partial reconfiguration of Xilinx Virtex-4 FPGAs, Javier Castillo
    • Re: dynamic partial reconfiguration of Xilinx Virtex-4 FPGAs, Peter Alfke
      • Re: dynamic partial reconfiguration of Xilinx Virtex-4 FPGAs, Stephane
      • Re: dynamic partial reconfiguration of Xilinx Virtex-4 FPGAs, Javier Castillo
• 8.1i SP2 download problems, Brian Davis
  • Re: 8.1i SP2 download problems, Antti
    • Re: 8.1i SP2 download problems, Brian Davis
  • Re: 8.1i SP2 download problems, Jon Beniston
• is there a way to initialize signals to a value, Matt Clement
  • Re: is there a way to tri-state outputs, Matt Clement
  • Re: is there a way to initialize signals to a value, GaLaKtIkUs?
  • Re: is there a way to initialize signals to a value, radarman
    • Re: is there a way to initialize signals to a value, Aurelian Lazarut
      • Re: is there a way to initialize signals to a value, Matt Clement
      • Re: is there a way to initialize signals to a value, Aurelian Lazarut
• XPower report precision, the . gaffar
  • Re: XPower report precision, Aurelian Lazarut
    • Re: XPower report precision, the . gaffar
      • Re: XPower report precision, Brendan Cullen
      • Re: XPower report precision, the . gaffar
      • Re: XPower report precision, the . gaffar
• Which SelectIO for FPGA <-> FPGA buses?, Pete Robinson
  • Re: Which SelectIO for FPGA <-> FPGA buses?, Brannon
• ModelSim Licence problem, Sonali
  • Re: ModelSim Licence problem, GaLaKtIkUs?
  • Re: ModelSim Licence problem, Kolja Sulimma
• ModelSim License Problem, Sonali
• Block vs. Distributed RAMs, bhatti1127
  • Re: Block vs. Distributed RAMs, Sylvain Munaut <SomeOne@xxxxxxxxxxxxxx>
• Dual Port Block RAM Inference, Yaseen Zaidi
• Entity with Multiple Architectures, Sudhir . Singh
  • Re: Entity with Multiple Architectures, backhus
• I2C and posedge sampling, svasus
  • Re: I2C and posedge sampling, Jim Granville
  • Re: I2C and posedge sampling, John_H
  • Re: I2C and posedge sampling, svasus
• Problem programming Altera flex 10k100 & EPC2, radarman
  • Re: Problem programming Altera flex 10k100 & EPC2, Hal Murray
    • Re: Problem programming Altera flex 10k100 & EPC2, radarman
• EDK Simulation, motty
• microblaze with FSL, upforever
  • Re: microblaze with FSL, siva.velusamy@xxxxxxxxx
    • Re: microblaze with FSL, upforever
• "does not fanout" warnings with inouts, shawnn
• Altera RoHS Irony, Al Clark
  • Re: Altera RoHS Irony, Jim Granville
  • Re: Altera RoHS Irony, Hul Tytus
    • Re: Altera RoHS Irony, rickman
      • Re: Altera RoHS Irony, David Brown
      • Re: Altera RoHS Irony, rickman
      • Re: Altera RoHS Irony, Al Clark
      • Re: Altera RoHS Irony, Nial Stewart
      • Re: Altera RoHS Irony, Al Clark
      • Re: Altera RoHS Irony, Dave Greenfield
      • Re: Altera RoHS Irony, Al Clark
      • Re: Altera RoHS Irony, rickman
      • Re: Altera RoHS Irony, Jim Granville
      • Re: Altera RoHS Irony, PeteS
      • Re: Altera RoHS Irony, Al Clark
      • Re: Altera RoHS Irony, David Brown
      • Re: Altera RoHS Irony, Luc
      • Re: Altera RoHS Irony, nospam
      • Re: Altera RoHS Irony, David Brown
      • Re: Altera RoHS Irony, nospam
      • Re: Altera RoHS Irony, David Brown
      • Re: Altera RoHS Irony, Markus Meng
  • Re: Altera RoHS Irony, Fredrik
    • Re: Altera RoHS Irony, kevinjwhite
• SCHEMATICS ... Is anybody as frustrated as I am with the software?, richard
  • Re: SCHEMATICS ... Is anybody as frustrated as I am with the software?, JJ
  • Re: SCHEMATICS ... Is anybody as frustrated as I am with the software?, Mike Treseler
  • Re: SCHEMATICS ... Is anybody as frustrated as I am with the software?, Mark McDougall
    • Re: SCHEMATICS ... Is anybody as frustrated as I am with the software?, Andrew Ward
      • Re: SCHEMATICS ... Is anybody as frustrated as I am with the software?, Jeff Cunningham
      • Re: SCHEMATICS ... Is anybody as frustrated as I am with the software?, Andrew Ward
      • Re: SCHEMATICS ... Is anybody as frustrated as I am with the software?, Symon
      • Re: SCHEMATICS ... Is anybody as frustrated as I am with the software?, Ray Andraka
      • Re: SCHEMATICS ... Is anybody as frustrated as I am with the software?, Symon
      • Re: SCHEMATICS ... Is anybody as frustrated as I am with the software?, Jim Granville
      • Re: SCHEMATICS ... Is anybody as frustrated as I am with the software?, fpga_toys
      • Message not available
      • Re: SCHEMATICS ... Is anybody as frustrated as I am with the software?, Symon
      • Message not available
      • Re: SCHEMATICS ... Is anybody as frustrated as I am with the software?, Symon
      • Message not available
      • Re: SCHEMATICS ... Is anybody as frustrated as I am with the software?, Ben Jones
    • state-of-the-art schematic generation? [Was: SCHEMATICS ... ], Adam Megacz
      • Re: state-of-the-art schematic generation? [Was: SCHEMATICS ... ], Bob Perlman
      • Re: state-of-the-art schematic generation? [Was: SCHEMATICS ... ], JJ
      • Re: state-of-the-art schematic generation? [Was: SCHEMATICS ... ], Alex Gibson
  • Re: SCHEMATICS ... Is anybody as frustrated as I am with the software?, PeteS
  • Re: SCHEMATICS ... Is anybody as frustrated as I am with the software?, aan.woodz@xxxxxxxxx
  • Re: SCHEMATICS ... Is anybody as frustrated as I am with the software?, Hendra
• Question about using LMB to connect BRAM in MicroBlaze, fpga
  • Re: Question about using LMB to connect BRAM in MicroBlaze, Antti Lukats
    • Re: Question about using LMB to connect BRAM in MicroBlaze, fpga
• Rocketio, modelsim xe, ndt
  • Re: Rocketio, modelsim xe, Gerhard Hoffmann
  • Re: Rocketio, modelsim xe, beeraka@xxxxxxxxx
• spartan-3e starter kit, Tom Dahlen
  • Re: spartan-3e starter kit, elf_ster
    • Re: spartan-3e starter kit, Eric Smith
    • Re: spartan-3e starter kit, John_H
      • Re: spartan-3e starter kit, Tom Dahlen
      • Re: spartan-3e starter kit, Antti
• xilinx ise 8.1 mig 1.4 /1.5, guy
• [ANN] MicroBlaze uClinux FPGA module (with microwindows) at Embedded, Antti
  • Re: [ANN] MicroBlaze uClinux FPGA module (with microwindows) at Embedded, Uwe Bonnes
    • Re: MicroBlaze uClinux FPGA module (with microwindows) at Embedded, Antti
• How to decode FAR register in Virtex-4?, Bertrand Rousseau
  • Re: How to decode FAR register in Virtex-4?, Stephane
    • Re: How to decode FAR register in Virtex-4?, Bertrand Rousseau
      • Re: How to decode FAR register in Virtex-4?, Sylvain Munaut <SomeOne@xxxxxxxxxxxxxx>
      • Re: How to decode FAR register in Virtex-4?, Bertrand Rousseau
      • Re: How to decode FAR register in Virtex-4?, Bertrand Rousseau
      • Re: How to decode FAR register in Virtex-4?, Sylvain Munaut <SomeOne@xxxxxxxxxxxxxx>
• Newb question about Xilinx Impact and parallel cable III ...., :-)
  • Re: Newb question about Xilinx Impact and parallel cable III ...., PeteS
    • Re: Newb question about Xilinx Impact and parallel cable III ...., :-)
      • Re: Newb question about Xilinx Impact and parallel cable III ...., :-)
      • Re: Newb question about Xilinx Impact and parallel cable III .... Solution found :-), :-)
• PacoBlaze updated, Pablo Bleyer Kocik
  • Re: PacoBlaze updated, Allan Herriman
    • Re: PacoBlaze updated, Pablo Bleyer Kocik
• Xilinx + I2C + PPC -> crash, matt
• digital logic library by 74xxxx part number?, aiiadict
  • Re: digital logic library by 74xxxx part number?, Slurp
  • Re: digital logic library by 74xxxx part number?, aiiadict
    • Re: digital logic library by 74xxxx part number?, richard
    • Re: digital logic library by 74xxxx part number?, backhus
      • Re: digital logic library by 74xxxx part number?, richard
      • Re: digital logic library by 74xxxx part number?, Andy Peters
      • Re: digital logic library by 74xxxx part number?, Slurp
      • Re: digital logic library by 74xxxx part number?, Peter Alfke
      • Re: digital logic library by 74xxxx part number?, Hal Murray
      • Re: digital logic library by 74xxxx part number?, Peter Alfke
      • Re: digital logic library by 74xxxx part number?, Andy Peters
      • Re: digital logic library by 74xxxx part number?, Peter Alfke
      • Re: digital logic library by 74xxxx part number?, Mike Treseler
      • Re: digital logic library by 74xxxx part number?, Jan Panteltje
      • Re: digital logic library by 74xxxx part number?, Jeff Cunningham
      • Re: digital logic library by 74xxxx part number?, jboothbee
      • Re: digital logic library by 74xxxx part number?, Mike Treseler
• spartan3 starter kit., zhangweidai
  • Re: spartan3 starter kit., aiiadict
    • Re: spartan3 starter kit., zhangweidai
  • Re: spartan3 starter kit., Hal Murray
    • Re: spartan3 starter kit., Symon
      • Re: spartan3 starter kit., Mike Harrison
      • Re: spartan3 starter kit., Symon
      • Re: spartan3 starter kit., Mike Harrison
      • Re: spartan3 starter kit., John Adair
      • Re: spartan3 starter kit., Symon
• Spartan3 configuration, Piotr Wyderski
• schematic capture, aiiadict
• Re: SDRAM Controller, Remis Norvilis
• Simulation problem using CONV_INTEGER, Giox
  • Re: Simulation problem using CONV_INTEGER, Dan NITA
  • Re: Simulation problem using CONV_INTEGER, Brian Drummond
• using FPGA in control field, wicky
  • Re: using FPGA in control field, Tim Wescott
    • Re: using FPGA in control field, wicky
      • Re: using FPGA in control field, fpga_toys
  • Re: using FPGA in control field, Gary Pace
    • Re: using FPGA in control field, Ray Andraka
      • Re: using FPGA in control field, Tim Wescott
    • Re: using FPGA in control field, wicky
  • Re: using FPGA in control field, kdfake@xxxxxxxx
    • Re: using FPGA in control field, wicky
• which one among the available FPGAs is best for a fresher?, chaitu11311@xxxxxxxxx
  • Re: which one among the available FPGAs is best for a fresher?, John Adair
    • Re: which one among the available FPGAs is best for a fresher?, fpga_toys
  • Re: which one among the available FPGAs is best for a fresher?, Hal Murray
  • Re: which one among the available FPGAs is best for a fresher?, Jerry Coffin
    • Re: which one among the available FPGAs is best for a fresher?, John Adair
      • Re: which one among the available FPGAs is best for a fresher?, John Adair
  • Re: which one among the available FPGAs is best for a fresher?, Herman Dullink
• LVDS, maxascent
  • Re: LVDS, Allan Herriman
  • Re: LVDS, dp
    • Re: LVDS, maxascent
• Creating low freq. clock on Altera FPGA, avishay
  • Re: Creating low freq. clock on Altera FPGA, Peter Alfke
  • Re: Creating low freq. clock on Altera FPGA, PeteS
• Re: FPGA-Programmable power supply, wicky
• Using Ethernet to control/initialize FPGA, James Ma
• Xilinx 1.5v HSTL-I for QDR-II. Anybody successful with it?, Ray Andraka
  • Re: Xilinx 1.5v HSTL-I for QDR-II. Anybody successful with it?, John Adair
  • Re: Xilinx 1.5v HSTL-I for QDR-II. Anybody successful with it?, Roger
    • Re: Xilinx 1.5v HSTL-I for QDR-II. Anybody successful with it?, Ray Andraka
      • Re: Xilinx 1.5v HSTL-I for QDR-II. Anybody successful with it?, Roger
      • Re: Xilinx 1.5v HSTL-I for QDR-II. Anybody successful with it?, Ray Andraka
      • Re: Xilinx 1.5v HSTL-I for QDR-II. Anybody successful with it?, MikeJ
• SMP on virtex-ii pro, Eric
  • Re: SMP on virtex-ii pro, John Williams
• SHARCS 2006, info@xxxxxxxxxx
• Spartan-3 Serial LVDS max speed?, Eric
• Altera EPLD, Sky
  • Re: Altera EPLD, Noway2
  • Re: Altera EPLD, Rene Tschaggelar
    • Re: Altera EPLD, Noway2
      • Re: Altera EPLD, Sky
      • Re: Altera EPLD, Rene Tschaggelar
      • Re: Altera EPLD, Carl Smith
      • Re: Altera EPLD, Jim Granville
      • Re: Altera EPLD, Andy Peters
  • Re: Altera EPLD, Philip Freidin
  • Re: Altera EPLD, Teo
• ANTTI*HAPPY: building MicroBlaze uClinux on WinXP full sucess !!, Antti
  • Re: ANTTI*HAPPY: building MicroBlaze uClinux on WinXP full sucess !!, Amontec, Larry
  • Re: ANTTI*HAPPY: building MicroBlaze uClinux on WinXP full sucess !!, Paul Hartke
    • Re: ANTTI*HAPPY: building MicroBlaze uClinux on WinXP full sucess !!, Antti
• Spartan3 embedded synchronous multipliers, Isaac Bosompem
  • Re: Spartan3 embedded synchronous multipliers, austin
  • Re: Spartan3 embedded synchronous multipliers, Marlboro
  • Re: Spartan3 embedded synchronous multipliers, Steve Knapp (Xilinx Spartan-3 Generation FPGAs)
    • Re: Spartan3 embedded synchronous multipliers, Isaac Bosompem
      • Re: Spartan3 embedded synchronous multipliers, Peter Alfke
• Simulation of MicroBlaze embedded system, motty
  • Re: Simulation of MicroBlaze embedded system, Paul Hartke
    • Re: Simulation of MicroBlaze embedded system, me_2003
      • Re: Simulation of MicroBlaze embedded system, motty
      • Re: Simulation of MicroBlaze embedded system, Paul Hartke
      • Re: Simulation of MicroBlaze embedded system, motty
• Xilinx ISERDES Q1 issues, Brad Smallridge
  • Re: Xilinx ISERDES Q1 issues, Brad Smallridge
  • Re: Xilinx ISERDES Q1 issues, Brad Smallridge
• Lattice new ECP2 parts, rickman
• Need help with generating video patterns using VHDL, methi
  • Re: Need help with generating video patterns using VHDL, John_H
    • Re: Need help with generating video patterns using VHDL, methi
      • Re: Need help with generating video patterns using VHDL, John_H
      • Re: Need help with generating video patterns using VHDL, methi
• Lattice high-end devices announced after years of rumours..., Gabor
• OPB busmaster device, S.T.
• EDK - PLB/OPB Bus questions., me_2003
  • <Possible follow-ups>
  • EDK - PLB/OPB Bus questions., me_2003
    • Re: EDK - PLB/OPB Bus questions., Zara
      • Re: EDK - PLB/OPB Bus questions., me_2003
      • Re: EDK - PLB/OPB Bus questions.