Re: Xilinx padding LC numbers, how do you really feel about it?

fpga_toys@xxxxxxxxx wrote: 
Austin Lesea wrote:

OK, OK.  We have heard you.
As I said, Peter and I will do our best to influence "truth in counting."



Does that mean we will see either total power or derating curves for
LUT/FF toggles to define power and thermal limits as both a percentage
of active logic or size of the active design?


<snip>

Just so that I understand you (as someone watching from the peanut gallery) are you suggesting that there is not enough information to determine whether a heavily-loaded device will work? The maximum allowable junction temperature is in the data sheet, the heat transfer values are package-specicif so they're included in the package documentation. Since each I/O can handle such large currents, I'm assuming (I do nt know for certain) that the Vccint and Gnd pins can handle any current you push into the device. It *is* an engineering exercise to determine the power draw of any non-simple FPGA and provide an appropriate power and cooling environment or do you believe otherwise?

So... If someone can attach a heat-pipe cooling apparatus with 0.295 deg C/watt (recently seen for high ambient temperature CPU cooling) and a power supply capable of pushing in unlimited current, will the large devices just not work?

I love the idea of getting the information "clean" in the data sheet but I don't understand what information could be provided to an unsupervised newbie engineer biting off more of a design than he should be allowed to develop because he obviously doesn't have the experience to understand engineering tradeoff in programmable devices without clouding the datasheet with significant amounts of information of little interest to 98% of engineers who actually do their work with the information already at hand.

The arguement in this thread was that misleading numbers suck for engineers. Do you honestly believe that it's misleading not to hand-hold the engineer by applying 20 more pages of drivel that should be in app notes or analysis tools?

I'd really hate to see the attitude of communicating information to the data sheet's target audience effectively be hampered by the attitude that any engineer should be able to know everything about how to design FPGAs from the data sheet alone.

So, if you're not just venting because you blew up a board in the past because you didn't do a proper engineering job, WHAT information in a properly cooled, powered, analyzed FPGA design should NOT be in a decent application note but in every device data sheet? "Derating" doesn't float with me unless you have specific ideas on how this information should be effectively delivered in the technical document intended to communicate the details of the specific FPGA device family.

- John_H
.

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