Re: Spartan3 initialization with DSP

"Marco" <marco@xxxxxxxxxxx> schrieb im Newsbeitrag
news:1137516377.278102.203140@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
> Hi, I have to initialize a Spartan3 with a Blackfin DSP. I was thinking
> to connect the CCLK and DIN pins to the serial port of the DSP (SPORT),
> but while the DIN is dual-purpose, the CCLK is dedicated. I'll then
> need, when all properly configured, FPGA and DSP to communicate with
> the SPORT once again for the normal work of the board.
> Here comes the issue because the CCLK used for the initialization has
> to be substituted with the serial protocol clock (as long as the former
> is a dedicated one and no more available after start-up).
> What do you suggest me to do? To put the 2 clock of the Spartan3 on the
> same path to the input pin of the SPORT clock on the DSP side, keeping
> the normal clock on high impedance during the configuration, ie when
> the initialization clock works, and the opposite after the setup
> process?
> Anyone had to solve similar issues?
> Thanks in advance,
> Marco
>
2 options

1) use Spartan3e there CCLK is dual purpose
2) add user IO in parallel to CCLK to be able to use it after configuration,
the 'normal' clock is automatically tri stated when FPGA is not configured
so it want matter, as long as the DSP can pull prog_b to force
(re)configuration

--
Antti Lukats
http://www.xilant.com


.

Relevant Pages

  • Spartan3 initialization with DSP
    ... I have to initialize a Spartan3 with a Blackfin DSP. ... but while the DIN is dual-purpose, the CCLK is dedicated. ... Here comes the issue because the CCLK used for the initialization has ... To put the 2 clock of the Spartan3 on the ...
    (comp.arch.fpga)
  • Re: humble suggestion for Xilinx
    ... and/or adding some serious hysteresis on future ... On a pcb, CCLK is often a shared SPI clock, with lots of loads ... I'd hazard that the majority of FPGAs are used at a fraction of their ...
    (comp.arch.fpga)
  • Re: XIlinx Spartan 2E stuck in configuration mode
    ... clocks require SI engineering. ... Can we program the CCLK pin's behavior? ... use it at very low clock rates, you will still need to do the necessary ... I have not tried to design in a slow driver, but even if you can't find ...
    (comp.arch.fpga)
  • Re: DCM question
    ... an external oscillator) for both the DSP and my Spartan3. ... the DSP creates the 600MHz clock from the 25MHz. ... suggestion would be to use the DCM to go up from 25MHz to 50 or 60 MHz ... and the inter-clock jitter will be limited to that coming ...
    (comp.arch.fpga)
  • Re: DCM question
    ... an external oscillator) for both the DSP and my Spartan3. ... the DSP creates the 600MHz clock from the 25MHz. ... suggestion would be to use the DCM to go up from 25MHz to 50 or 60 MHz ... that it derives its internal clock from the one generated by the FPGA. ...
    (comp.arch.fpga)