Re: Easier initializing of blockram (spartan3)


"Ray Andraka" <ray@xxxxxxxxxxx> wrote in message
news:OBwwf.41652$Mi5.32734@xxxxxxxxxxxxx
> Morten Leikvoll wrote:
>> Instead of using INIT_XX=>"...." I would like to write like
>> "INIT(W,A)=>D" where W is the buswidth and D is the initial value
>> (including parity bus) at the port at adress A. This is a plain mapping
>> function and maybe someone has done this before me so I dont have to
>> rewrite it?
>>
>>
> You still need the init_xx= attributes , however you can put the primitive
> inside a wrapper and write a set of functions to deconstruct an integer
> array passed as a generic and generate the proper init_xx attributes. You
> can even handle data split across multiple BRAMs this way.
>
> Do it with a vhdl function (I am assuming you are using VHDL, this would
> be really ugly with verilog) that accepts the data array (array of
> integers, passed into your wrapper as a generic), an index which
> corresponds to the XX in INIT_XX, and the msb and lsb of the slice the
> function is to generate. From the widht of the field (msb:lsb) you can
> infer the length of the output bit vector, as well as the address into
> your integer array that holds the data. The output of the function is a
> bit vector to match the generic on the BRAM primitive. You can write a
> second function to convert the bit vector to the hex string needed for the
> attribute.

I'm not sure if I can get it to work with arrays as I dont know how to pass
these parameters several times using the same name... Maybe something will
pop up in my head.

I just tried this.. It compiles but I have yet to verify if the bit
shuffling is ok. I use one side as an instruction word of 36bit (32+4
parity) and want to initialize a program for simulation. This should be in
the default libraries for all BRAM configurations.
Warning:ugly formatted long-line code follows:

entity RAMB16_S9_S36i is
generic
(
init_000:bit_vector(35 downto 0):=(others=>'0');
init_001:bit_vector(35 downto 0):=(others=>'0');
[...... stuff deleted....]
init_1FF:bit_vector(35 downto 0):=(others=>'0')
);
Port
(
DOA : out std_logic_vector(7 downto 0);
DOB : out std_logic_vector(31 downto 0);
DOPA : out std_logic_vector(0 downto 0);
DOPB : out std_logic_vector(3 downto 0);
ADDRA : in std_logic_vector(10 downto 0);
ADDRB : in std_logic_vector(8 downto 0);
CLKA : in std_logic;
CLKB : in std_logic;
DIA : in std_logic_vector(7 downto 0);
DIB : in std_logic_vector(31 downto 0);
DIPA : in std_logic_vector(0 downto 0);
DIPB : in std_logic_vector(3 downto 0);
ENA : in std_logic;
ENB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
WEA : in std_logic;
WEB : in std_logic
);
end RAMB16_S9_S36i;

architecture Behavioral of RAMB16_S9_S36i is

constant INIT00 :bit_vector(255 downto 0):= init_007(31 downto 0) &
init_006(31 downto 0) & init_005(31 downto 0) & init_004(31 downto 0) &
init_003(31 downto 0) & init_002(31 downto 0) & init_001(31 downto 0) &
init_000(31 downto 0);
constant INIT01 :bit_vector(255 downto 0):= init_00F(31 downto 0) &
init_00E(31 downto 0) & init_00D(31 downto 0) & init_00C(31 downto 0) &
init_00B(31 downto 0) & init_00A(31 downto 0) & init_009(31 downto 0) &
init_008(31 downto 0);
[...... stuff deleted....]
constant INIT3F :bit_vector(255 downto 0):= init_1FF(31 downto 0) &
init_1FE(31 downto 0) & init_1FD(31 downto 0) & init_1FC(31 downto 0) &
init_1FB(31 downto 0) & init_1FA(31 downto 0) & init_1F9(31 downto 0) &
init_1F8(31 downto 0);

constant INITP00:bit_vector(255 downto 0):=
init_007(35 downto 32) & init_006(35 downto 32) & init_005(35 downto 32)
& init_004(35 downto 32) & init_003(35 downto 32) & init_002(35 downto 32) &
init_001(35 downto 32) & init_000(35 downto 32)&
init_00F(35 downto 32) & init_00E(35 downto 32) & init_00D(35 downto 32)
& init_00C(35 downto 32) & init_00B(35 downto 32) & init_00A(35 downto 32) &
init_009(35 downto 32) & init_008(35 downto 32)&
init_017(35 downto 32) & init_006(35 downto 32) & init_005(35 downto 32)
& init_004(35 downto 32) & init_003(35 downto 32) & init_002(35 downto 32) &
init_001(35 downto 32) & init_000(35 downto 32)&
init_01F(35 downto 32) & init_00E(35 downto 32) & init_00D(35 downto 32)
& init_00C(35 downto 32) & init_00B(35 downto 32) & init_00A(35 downto 32) &
init_009(35 downto 32) & init_008(35 downto 32)&
init_027(35 downto 32) & init_026(35 downto 32) & init_025(35 downto 32)
& init_024(35 downto 32) & init_023(35 downto 32) & init_022(35 downto 32) &
init_021(35 downto 32) & init_020(35 downto 32)&
init_02F(35 downto 32) & init_02E(35 downto 32) & init_02D(35 downto 32)
& init_02C(35 downto 32) & init_02B(35 downto 32) & init_02A(35 downto 32) &
init_029(35 downto 32) & init_028(35 downto 32)&
init_037(35 downto 32) & init_036(35 downto 32) & init_035(35 downto 32)
& init_034(35 downto 32) & init_033(35 downto 32) & init_032(35 downto 32) &
init_031(35 downto 32) & init_030(35 downto 32)&
init_03F(35 downto 32) & init_03E(35 downto 32) & init_03D(35 downto 32)
& init_03C(35 downto 32) & init_03B(35 downto 32) & init_03A(35 downto 32) &
init_039(35 downto 32) & init_038(35 downto 32);

[...... more stuff deleted....]
constant INITP07:bit_vector(255 downto 0):=
init_1C7(35 downto 32) & init_1C6(35 downto 32) & init_1C5(35 downto 32)
& init_1C4(35 downto 32) & init_1C3(35 downto 32) & init_1C2(35 downto 32) &
init_1C1(35 downto 32) & init_1C0(35 downto 32)&
init_1CF(35 downto 32) & init_1CE(35 downto 32) & init_1CD(35 downto 32)
& init_1CC(35 downto 32) & init_1CB(35 downto 32) & init_1CA(35 downto 32) &
init_1C9(35 downto 32) & init_1C8(35 downto 32)&
init_1D7(35 downto 32) & init_1D6(35 downto 32) & init_1D5(35 downto 32)
& init_1D4(35 downto 32) & init_1D3(35 downto 32) & init_1D2(35 downto 32) &
init_1D1(35 downto 32) & init_1D0(35 downto 32)&
init_1DF(35 downto 32) & init_1DE(35 downto 32) & init_1DD(35 downto 32)
& init_1DC(35 downto 32) & init_1DB(35 downto 32) & init_1DA(35 downto 32) &
init_1D9(35 downto 32) & init_1D8(35 downto 32)&
init_1E7(35 downto 32) & init_1E6(35 downto 32) & init_1E5(35 downto 32)
& init_1E4(35 downto 32) & init_1E3(35 downto 32) & init_1E2(35 downto 32) &
init_1E1(35 downto 32) & init_1E0(35 downto 32)&
init_1EF(35 downto 32) & init_1EE(35 downto 32) & init_1ED(35 downto 32)
& init_1EC(35 downto 32) & init_1EB(35 downto 32) & init_1EA(35 downto 32) &
init_1E9(35 downto 32) & init_1E8(35 downto 32)&
init_1F7(35 downto 32) & init_1F6(35 downto 32) & init_1F5(35 downto 32)
& init_1F4(35 downto 32) & init_1F3(35 downto 32) & init_1F2(35 downto 32) &
init_1F1(35 downto 32) & init_1F0(35 downto 32)&
init_1FF(35 downto 32) & init_1FE(35 downto 32) & init_1FD(35 downto 32)
& init_1FC(35 downto 32) & init_1FB(35 downto 32) & init_1FA(35 downto 32) &
init_1F9(35 downto 32) & init_1F8(35 downto 32);

begin

RAMB16_S9_S36_inst : RAMB16_S9_S36
generic map
(
INIT_A => X"000", -- Value of output RAM registers on Port A at startup
INIT_B => X"000000000", -- Value of output RAM registers on Port B at
startup
SRVAL_A => X"000", -- Port A ouput value upon SSR assertion
SRVAL_B => X"000000000", -- Port B ouput value upon SSR assertion

INIT_00 => INIT00,
INIT_01 => INIT01,
[...... even more stuff deleted....]
INIT_3F => INIT3F,

INITP_00 =>INITP00,
INITP_01 =>INITP01,
INITP_02 =>INITP02,
INITP_03 =>INITP03,
INITP_04 =>INITP04,
INITP_05 =>INITP05,
INITP_06 =>INITP06,
INITP_07 =>INITP07
)
port map
(
DOA => DOA, -- Port A 8-bit Data Output
DOB => DOB, -- Port B 32-bit Data Output
DOPA => DOPA, -- Port A 1-bit Parity Output
DOPB => DOPB, -- Port B 4-bit Parity Output
ADDRA => ADDRA, -- Port A 11-bit Address Input
ADDRB => ADDRB, -- Port B 9-bit Address Input
CLKA => CLKA, -- Port A Clock
CLKB => CLKB, -- Port B Clock
DIA => DIA, -- Port A 8-bit Data Input
DIB => DIB, -- Port B 32-bit Data Input
DIPA => DIPA, -- Port A 1-bit parity Input
DIPB => DIPB, -- Port-B 4-bit parity Input
ENA => ENA, -- Port A RAM Enable Input
ENB => ENB, -- PortB RAM Enable Input
SSRA => SSRA, -- Port A Synchronous Set/Reset Input
SSRB => SSRB, -- Port B Synchronous Set/Reset Input
WEA => WEA, -- Port A Write Enable Input
WEB => WEB -- Port B Write Enable Input
);
end Behavioral;



.

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