Re: Beginner help with VHDL, Xilinx 9536XL, and ISE7.1

cdsmith69@xxxxxxxxx wrote: 
So I need some help getting started with programmable logic and VHDL.

It shouldn't be this difficult...

My guess is that you haven't defined which pin on the outside of your CPLD is connected to which signal on the inside of your CPLD. You've ended up with random signals to random pins, defined by the fitting tool to whatever made it's life easiest. The mapping will change every time you modify and resysnthesise the code.

You need to add a .ucf file to your project with the signal->pin mappings in it. It's just a text file, the format should look something similar to the following:

# DSP bus interface
NET "XA<0>" 	LOC = "p128";
NET "XA<1>" 	LOC = "p102";
NET "XA<2>" 	LOC = "p89";
NET "XINT1"	LOC = "p130";
NET "CSn"	LOC = "p100";
NET "RDn"	LOC = "p103";

The .ucf file is also where you add your timing constraints, you should at least have one for your clock (when you're using one). That section will look like:

# Timing constraints
NET "CLOCK" TNM_NET = "CLOCK";
TIMESPEC "TS_CLOCK" = PERIOD "CLOCK" 8 ns HIGH 50 %;
NET "CLOCK" USELOWSKEWLINES;

These constraints have been cut from an FPGA project .ucf file, but I'm pretty sure that the syntax is the same for CPLDs.

Hope this helps!

Cheers,
James
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