Re: Start up condition of flip flops in FPGA?

Sometimes you need defined outputs even if there is no clock. In such
cases, pulling the prog line low may not cut it. In such cases, an
asynchronously asserted, and syncrhonously deasserted, asynchronous
reset is the safest option.

But, like Ray said, you often don't need reset everywhere.

As to the initial values after configuration, remember that the end of
configuration is likely to be asynchronous to your clock, so for
example, a down counter initialized to a zero may not be a good idea!
In general, down counters should be initialized to odd values, and up
counters should be initialised to even values, to avoid having an
uncertainty in more than one bit (the LSB) on the first clock at/after
reset/config.

For synchronous deassertion of asynchronous resets, another option is
to disable the clock until several periods after reset is deasserted,
giving it time to propagate to all targets.

Andy

.

Relevant Pages

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