Re: Serious Typo in the Xilinx Floating-Point Core Manual?
- From: "walke" <richard.walke@xxxxxxxxxx>
- Date: 4 Jan 2006 09:01:27 -0800
No this is not a typo, and yes, it does not make sense, and so this
variant has been removed from v2.0 of the Xilinx floating-point
operator core. (Note that the logic multiplier uses an optimized
multiplier and so is pretty good in its utilization of resources).
The release of v2.0 is imminent, and the 4x DSP single precision
multiplier will be much faster and use less slices that v1.0.
Thanks,
Richard Walke
Robin Bruce wrote:
> http://www.xilinx.com/bvdocs/ipcenter/data_sheet/floating_point.pdf
>
> With regard to the speed-optimised single-precision floating-point
> core, look at:
>
> Table 6: Latency of Speed Optimized Core (Page 10)
> Table 10: Characterization of Speed-Optimized Single-Precision Core
> (Page 18)
>
> These are the characteristics of the speed-optimised floating-point
> cores from Xilinx. For virtex-4 there's a multiplier version that
> uses a single DSP48 block, as opposed to the standard 4x DSP48 version.
> My question is: What's the point of it? There's a pure logic one
> there that uses less slices, has a lower latency and operates
> as-near-as-damn-it at the same frequency. More to the point you're not
> throwing away a DSP48...
>
> I've spoken to colleagues about this, and the best guess we can come to
> is that there's a typo, most likely on the slice count for the single
> DSP48 + slices version. Anyone know better?
>
> Cheers,
>
> Robin Bruce
.
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