FSM goes into invalid state after reset...

I have a design that is a one hot FSM.
Sometime the FSM was locked up invalid state after reset. But I had set
the default state.
Does anyone have any idea on how this could happen ?

Thanks

My design is as follows,
-------------------------------------------------
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
cur_state <= IDLE;
else
cur_state <= next_state;
end

always @(*) beign
case (cur_state)
IDLE: next_state = ST1;
.
.
.
default: next_state = IDLE;
endcase
end

.

Relevant Pages

  • Re: Need for reset in FPGAs
    ... usually a reset signal is applied to put the FFs of an FPGA into a known ... Whether or not you need a reset depends on your design and the ... that are asynchronous to the FSM clock. ...
    (comp.arch.fpga)
  • Re: Out of memory error in Synplicity
    ... kb33 wrote: ... I am trying to synthesize my design (it has FSM and for loops inside ...
    (comp.lang.verilog)
  • Re: C# and Spartan 3 Starter Kit
    ... As a former senior design project lab instructor, let me give you a few ... and got stuck debugging unnecessary problems. ... interfaces with little more than an FSM and a ROM. ...
    (comp.arch.fpga)
  • Out of memory error in Synplicity
    ... I am trying to synthesize my design (it has FSM and for loops inside ... The target FPGA is Xilinx Virtex 2 XC2V6000. ...
    (comp.lang.verilog)
  • Re: Test Driven Development Sample
    ... One interesting issue is that the FSM design is an adjunct to the ... The original bowling game code still ... Object Mentor Inc. | unclebob @ objectmentor. ...
    (comp.object)