Re: Going insane - Xilinx VGA controller...

peter.halford@xxxxxxxxxxx wrote: 
Dear Group,

I am designing an LCD controller, straight VGA using a 6.5" TFT (60Hz
and a 25MHz dot clock) with a 32MBit SDRAM frame buffer (using two
Xilinx block RAMs as alternate line buffers).

Xilinx ISE 7.1 development environment.

I also designed the hardware: a BlackFin BF532 CPU/ROM/SDRAM with a
Xilinx Spartan-3 (XC3S400-4PQ208C) handling the general I/F
requirements and VGA display. It is a 4-layer PCB with a 25MHz master
clock.

Until now, all my coding has been with VHDL and everything has
simulated correctly.

Come on now... Just how difficult can it be? Or so I thought.

Well, everything works just fine for about 200ms (correct syncs etc...)
and then things go dead for 800ms -- no syncs, nothing. And then things
spring back to life for another 200ms ad nauseam...

The internal clocks are running fine (I have some spare signals on the
FPGA to which I can bind some debug signals).

Since I am pretty much a newbie to VHDL, I figured I would design a
replacement VGA module using gate-level logic (counters, comparators
and so on)  but it generates exactly the same results.

The power supplies appear to be clean. The BlackFin continues to work
with a command-line UBOOT serial link.

This project has taken 6-weeks longer than it needed to. I look an
idiot (which I probably am) and only the thought of how much pleasure
it would give my mother-in-law stops me from 'doing myself in'...

Any kind or informative suggestions would be very much appreciated.

Regards & seasonal greetings to all.

As you seem to have a behaving system some of the time, lock onto that, and expand on what you DO know - viz: try and be get better values for the 200ms and 800ms - things like how many frames, exactly; and is it a precise 1 second repeat. and how dead is dead.. Syncs gone, or changed, ? (etc)
Are the syncs precisely correct ? - it's not something like the montior just not quite being able to hold-onto things ?

 That's many, many frames, so sounds unlike a gate level issue.

Then look around at what it is in the system that changes at precisely those times....

 -jg

.

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