Re: Simulating Post-Synthesis Model on Xilinx FPGA
- From: "Chloe" <chloe_music2003@xxxxxxxxxxx>
- Date: 8 Dec 2005 19:16:34 -0800
Oh really? Apologies for my ignorance. This is my first time using an
FPGA's synthesis tool, so I didn't know that synthesis actually meant
translate and map. I thought translate and map was using the LOCed pin
assignments and inserting that with the synthesised design onto the
FPGA. I previously dealt with Synopsys synthesis tool, Design Compiler,
so it's a little different from FPGA synthesis.
Anyways, I am having a little trouble with the design on FPGA. When I
simulated the behavioural model on ModelSim, the results are correct.
However, after synthesis, when I ran a simulation on the post-translate
verilog model, the outputs were wrong. Ditto for post-map and post-PAR
verilog models.
I'm at my wits' end, because I've been working on the problem for quite
some time now, and yet, I still couldn not find the root of the
problem. There were no errors in my synthesis report, translate report,
map report and PAR report. There were no timing violations either.
Any suggestions for an FPGA rookie like me?
Oh, by the way, I think it's more like "After I leave, but before I get
there" ;)
Thanks in advance.
.
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