comp.arch.fpga

• Date Index

---

• Timing problem in ModelSim, Post-Route Simulation., Dan NITA
  • Re: Timing problem in ModelSim, Post-Route Simulation., Julian Kain
• Low cost PCI FPGA cards for reconfigurable computing, Totally_Lost
  • Re: Low cost PCI FPGA cards for reconfigurable computing, Antti Lukats
  • Re: Low cost PCI FPGA cards for reconfigurable computing, John Adair
• Fitting circuits to fpga LUTs, Totally_Lost
• open source xnf to edif script, Totally_Lost
• Newbie question - using library "design elements", Mike Oxlarge
  • Re: Newbie question - using library "design elements", John Adair
    • Re: Newbie question - using library "design elements", Mike Oxlarge
      • Re: Newbie question - using library "design elements", John Adair
• Easy and fun: Worlds smallest FPGA module., Antti Lukats
• How do I instantiate an ADSU8 in ISE7.1i?, Paul Marciano
  • Re: How do I instantiate an ADSU8 in ISE7.1i?, Antti Lukats
• using internal POR, drg
  • Re: using internal POR, Antti Lukats
• Can some give me some advice?, bjzhangwn
  • Re: Can some give me some advice?, JJ
  • Re: Can some give me some advice?, Tim Wescott
• call for papers,Expresscard specification?, bjzhangwn
  • Re: call for papers,Expresscard specification?, Antti Lukats
  • Re: call for papers,Expresscard specification?, bjzhangwn
    • Re: call for papers,Expresscard specification?, Antti Lukats
    • Re: call for papers,Expresscard specification?, Hans
  • Re: call for papers,Expresscard specification?, John Adair
• call for papers,Expresscard?, bjzhangwn
• TCL SCRIPT AND VHDL DESIGN, AAA
  • Re: TCL SCRIPT AND VHDL DESIGN, Hans
• PPC405 on ISE, king_azman
  • Re: PPC405 on ISE, Antti Lukats
  • Re: PPC405 on ISE, Duane Clark
• Brute Force Examination of a PLD, logjam
  • Re: Brute Force Examination of a PLD, Mike Harrison
  • Re: Brute Force Examination of a PLD, Henry
    • Re: Brute Force Examination of a PLD, Antti Lukats
      • Re: Brute Force Examination of a PLD, logjam
• Virtex 4 desing : ChipScope insertion impacts my timing problem debug, linq936
  • Re: Virtex 4 desing : ChipScope insertion impacts my timing problem debug, mike_la_jolla
  • Re: Virtex 4 desing : ChipScope insertion impacts my timing problem debug, John Adair
• Xilinx ML402 DRAM control, Brad Smallridge
  • Re: Xilinx ML402 DRAM control, Joseph Samson
• Actel Fusion, Martin Schoeberl
  • Re: Actel Fusion, Antti Lukats
• Spartan3E Parallel Flash Programming (with free Spartan 3e Sample Pack), Antti Lukats
  • Re: Spartan3E Parallel Flash Programming (with free Spartan 3e Sample Pack), Antti Lukats
    • Re: Spartan3E Parallel Flash Programming (with free Spartan 3e Sample Pack), Symon
      • Re: Spartan3E Parallel Flash Programming (with free Spartan 3e Sample Pack), Antti Lukats
• System Monitor in Virtex-4, Lars
  • Re: System Monitor in Virtex-4, Symon
    • Re: System Monitor in Virtex-4, Lars
      • Re: System Monitor in Virtex-4, Symon
      • Re: System Monitor in Virtex-4: alive? or dead? or just forgotten?, Austin Lesea
      • Re: System Monitor in Virtex-4: alive? or dead? or just forgotten?, Lars
• FSM goes into invalid state after reset..., akun
  • Re: FSM goes into invalid state after reset..., francesco_poderico
  • Re: FSM goes into invalid state after reset..., John Adair
• USB Printer Interface, Marco T.
  • Re: USB Printer Interface, Antti Lukats
    • Re: USB Printer Interface, Marco T.
• PCI interface on CYCLONE(ep1c6), eehinjor
  • Re: PCI interface on CYCLONE(ep1c6), PeteS
• Power Optimization: can the routing and placement really save power?, Austin Lesea
  • Re: Power Optimization: can the routing and placement really save power?, soar2morrow
    • Re: Power Optimization: can the routing and placement really save power?, Austin Lesea
  • Re: Power Optimization: can the routing and placement really save power?, PeteS
  • Re: Power Optimization: can the routing and placement really save power?, Martin Schoeberl
    • Re: Power Optimization: can the routing and placement really save power?, Symon
      • Re: Power Optimization: can the routing and placement really save power?, Martin Schoeberl
      • Re: Power Optimization: can the routing and placement really save power?, Peter Alfke
      • Re: Power Optimization: can the routing and placement really save power?, Martin Schoeberl
      • Re: Power Optimization: can the routing and placement really save power?, Peter Alfke
      • Re: Power Optimization: can the routing and placement really save power?, Jan Panteltje
      • Re: Power Optimization: can the routing and placement really save power?, Jim Granville
  • Re: Power Optimization: can the routing and placement really save power?, Jim Granville
    • Re: Power Optimization: can the routing and placement really save power?, Peter Alfke
• What is 'drive strength' for? (Spartan 3), Paul Boven
  • Re: What is 'drive strength' for? (Spartan 3), Austin Lesea
    • Re: What is 'drive strength' for? (Spartan 3), Sylvain Munaut
      • Re: What is 'drive strength' for? (Spartan 3), Austin Lesea
  • Re: What is 'drive strength' for? (Spartan 3), Kolja Sulimma
• Xilinx LVDS termination resistor, Brad Smallridge
  • Re: Xilinx LVDS termination resistor, Austin Lesea
    • Re: Xilinx LVDS termination resistor, Brad Smallridge
      • Re: Xilinx LVDS termination resistor, Marc Randolph
  • Re: Xilinx LVDS termination resistor, Brad Smallridge
• Lattice XP simple simulator, Piotr Wyderski
• CP2101 <-> Printer?, Marco T.
  • Re: CP2101 <-> Printer?, Antti Lukats
• ISE WebPack Clock Signals, u_stadler@xxxxxxxx
  • Re: ISE WebPack Clock Signals, sunyz
• Handel-C & DK3, camillo79
• DigitalRadioMondiale, Soenke
  • Re: DigitalRadioMondiale, Uncle Noah
• disappear silicore, eou4
• Can Altera Cyclone device's clock input directly used as CLK with PLL?, Binary
  • Re: Can Altera Cyclone device's clock input directly used as CLK with PLL?, eou4
  • Re: Can Altera Cyclone device's clock input directly used as CLK with PLL?, Rob
  • Re: Can Altera Cyclone device's clock input directly used as CLK with PLL?, Noway2
• S3e starter kits available, Alex Gibson
  • Re: S3e starter kits available, John_H
    • Re: S3e starter kits available, Antti Lukats
    • Re: S3e starter kits available, Joe Chisolm
      • Re: S3e starter kits available, Antti Lukats
      • Re: S3e starter kits available, Joe Chisolm
      • Re: S3e starter kits available, Antti Lukats
• serial configuration of Spartan 3 FPGA, Yaju Nagaonkar
• Using Synplicity to synthesize EDK user IP's, motty
  • Re: Using Synplicity to synthesize EDK user IP's, Mike Treseler
  • Re: Using Synplicity to synthesize EDK user IP's, Bob Efram
    • Re: Using Synplicity to synthesize EDK user IP's, motty
      • Re: Using Synplicity to synthesize EDK user IP's, motty
• Virtex-4 CCLK termination, shogmic
  • Re: Virtex-4 CCLK termination, Austin Lesea
  • Re: Virtex-4 CCLK termination, Brad Smallridge
  • Re: Virtex-4 CCLK termination, Peter Alfke
    • Re: Virtex-4 CCLK termination, Bob
      • Re: Virtex-4 CCLK termination, Peter Alfke
      • Re: Virtex-4 CCLK termination, Bob
      • Re: Virtex-4 CCLK termination, Peter Alfke
      • Re: Virtex-4 CCLK termination, shogmic
      • Re: Virtex-4 CCLK termination, Austin Lesea
      • Re: Virtex-4 CCLK termination, Bevan Weiss
      • Re: Virtex-4 CCLK termination, Peter Alfke
      • Re: Virtex-4 CCLK termination, Symon
      • Re: Virtex-4 CCLK termination, Austin Lesea
      • Re: Virtex-4 CCLK termination, Peter Alfke
      • Re: Virtex-4 CCLK termination, Symon
      • Re: Virtex-4 CCLK termination, Bob
• ERROR:iMPACT:585, Nitesh
  • Re: ERROR:iMPACT:585, Neil Glenn Jacobson
• USB 2.0 testbench available?, johnp
  • Re: USB 2.0 testbench available?, Antti Lukats
    • Re: USB 2.0 testbench available?, johnp
• Re: Xilinx Stepping Methodology, Ray Andraka
  • <Possible follow-ups>
  • Re: Xilinx Stepping Methodology, Austin Lesea
    • Message not available
      • Re: Xilinx Stepping Methodology, Austin Lesea
• DDR2 support for EDK, Antti Lukats
  • Re: DDR2 support for EDK, wtxwtx
    • Re: DDR2 support for EDK, Antti Lukats
• Microblaze in a EDK pcore, Cédric Jeanneret
  • Re: Microblaze in a EDK pcore, Antti Lukats
  • Re: Microblaze in a EDK pcore, Petter Gustad
  • Re: Microblaze in a EDK pcore, Paul Hartke
• Call for Papers: The 2006 IAENG International Workshop on Scientific Computing and Computational Statistics, imecs2006
• Download to board with RS232, Frank Schreiber
  • Re: Download to board with RS232, Rob
  • Re: Download to board with RS232, Antti Lukats
    • Re: Download to board with RS232, Martin Schoeberl
      • Re: Download to board with RS232, Antti Lukats
      • Re: Download to board with RS232, Martin Schoeberl
• Xilinx V4 LVDS, Brad Smallridge
  • Re: Xilinx V4 LVDS, Rob
    • Re: Xilinx V4 LVDS, Brad Smallridge
      • Re: Xilinx V4 LVDS, Rob
  • Re: Xilinx V4 LVDS, avishay
    • Re: Xilinx V4 LVDS, Brad Smallridge
  • Re: Xilinx V4 LVDS, Brad Smallridge
    • Re: Xilinx V4 LVDS, Rob
      • Re: Xilinx V4 LVDS, Brad Smallridge
      • Re: Xilinx V4 LVDS, Sean Durkin
      • Re: Xilinx V4 LVDS, Sean Durkin
      • Re: Xilinx V4 LVDS, Brad Smallridge
  • Re: Xilinx V4 LVDS, Brad Smallridge
• Spartan-3 Starter Kit newbie question, Olivier Scalbert
  • Re: Spartan-3 Starter Kit newbie question, Antti Lukats
    • Re: Spartan-3 Starter Kit newbie question, Olivier Scalbert
• IEEE package VHDL reference manual, Binary
  • Re: IEEE package VHDL reference manual, allanherriman
• Looking for 64 bit IEEE802.3 Verilog code or tips for code, Vik
  • Re: Looking for 64 bit IEEE802.3 Verilog code or tips for code, Philip Freidin
    • Re: Looking for 64 bit IEEE802.3 Verilog code or tips for code, Vik
• Spartan 3 power requirements, Piotr Wyderski
  • Re: Spartan 3 power requirements, Hal Murray
    • Re: Spartan 3 power requirements, Piotr Wyderski
  • Re: Spartan 3 power requirements, Peter Alfke
    • Re: Spartan 3 power requirements, Piotr Wyderski
      • Re: Spartan 3 power requirements, Peter Alfke
    • Re: Spartan 3 power requirements, Hal Murray
      • Re: Spartan 3 power requirements, Peter Alfke
      • Re: Spartan 3 power requirements, Peter Alfke
• how to use ICAP on Virtex-II XC2V1000-FG456-4?, lioupayphone@xxxxxxxxx
  • Re: how to use ICAP on Virtex-II XC2V1000-FG456-4?, Antti Lukats
• Re: More beginner's verilog questions, burn . sir
• Is the microblaze or nios2 free?, bjzhangwn
  • Re: Is the microblaze or nios2 free?, Antti Lukats
• Where to find the Altera Schematic, Binary
  • Re: Where to find the Altera Schematic, bjzhangwn
  • Re: Where to find the Altera Schematic, chenboya@xxxxxxxxx
• XILINX I2C controller core in FPGA and multisource problem., svasus
  • Re: XILINX I2C controller core in FPGA and multisource problem., wtxwtx
    • Re: XILINX I2C controller core in FPGA and multisource problem., Antti Lukats
      • Re: XILINX I2C controller core in FPGA and multisource problem., wtxwtx
      • Re: XILINX I2C controller core in FPGA and multisource problem., Antti Lukats
      • Re: XILINX I2C controller core in FPGA and multisource problem., wtxwtx
      • Re: XILINX I2C controller core in FPGA and multisource problem., Antti Lukats
      • Re: XILINX I2C controller core in FPGA and multisource problem., svasus
      • Re: XILINX I2C controller core in FPGA and multisource problem., wtxwtx
      • Re: XILINX I2C controller core in FPGA and multisource problem., Antti Lukats
      • Re: XILINX I2C controller core in FPGA and multisource problem., wtxwtx
      • Re: XILINX I2C controller core in FPGA and multisource problem., Uwe Bonnes
• Xilinx ISE Simulator, mail
  • Re: Xilinx ISE Simulator, Antti Lukats
  • Re: Xilinx ISE Simulator, Paul Hartke
    • Re: Xilinx ISE Simulator, mail
• Can somone work on the pci express project?, bjzhangwn
  • Re: Can somone work on the pci express project?, Tim Wescott
    • Re: Can somone work on the pci express project?, bjzhangwn
      • Re: Can somone work on the pci express project?, Kevin Brace
      • Re: Can somone work on the pci express project?, Antti Lukats
      • Re: Can somone work on the pci express project?, Kevin Brace
      • Re: Can somone work on the pci express project?, Antti Lukats
    • Re: Can somone work on the pci express project?, Kevin Brace
      • Re: Can somone work on the pci express project?, mk
• re:Does this group allow JobPostings?, kathy
• FREE Spartan 3e Sample Pack, Antti Lukats
• Image processing libraries and VHDL, john
  • Re: Image processing libraries and VHDL, Arne Demmers
• Virtex-4FX and ethernet mac, Marco T.
  • Re: Virtex-4FX and ethernet mac, Paul Hartke
  • re:Virtex-4FX and ethernet mac, leevv
    • Re: re:Virtex-4FX and ethernet mac, Jon Beniston
      • Re: re:Virtex-4FX and ethernet mac, Antti Lukats
  • Re: Virtex-4FX and ethernet mac, Marco T.
• SystemACE problem, Arne Demmers
• Spartan3e and ChipScope, Antti Lukats
  • Re: Spartan3e and ChipScope, Leon
    • Re: Spartan3e and ChipScope, Antti Lukats
      • Re: Spartan3e and ChipScope, Alex Gibson
      • Re: Spartan3e and ChipScope, Leon
      • Re: Spartan3e and ChipScope, Alex Gibson
    • Re: Spartan3e and ChipScope, Antti Lukats
  • Re: Spartan3e and ChipScope, Andy Peters
    • Re: Spartan3e and ChipScope, Antti Lukats
      • Re: Spartan3e and ChipScope, John McCaskill
      • Re: Spartan3e and ChipScope, Peter Alfke
      • Re: Spartan3e and ChipScope, Antti Lukats
    • Re: Spartan3e and ChipScope, Antti Lukats
• Is there anybody that have ported the linux to the nios or microblaze?, bjzhangwn
  • Re: Is there anybody that have ported the linux to the nios or microblaze?, Alex Gibson
    • Re: Is there anybody that have ported the linux to the nios or microblaze?, Antti Lukats
      • Re: Is there anybody that have ported the linux to the nios or microblaze?, Alex Gibson
      • Re: Is there anybody that have ported the linux to the nios or microblaze?, Paul Hartke
      • Re: Is there anybody that have ported the linux to the nios or microblaze?, bjzhangwn
      • Re: Is there anybody that have ported the linux to the nios or microblaze?, John McCaskill
    • Re: Is there anybody that have ported the linux to the nios or microblaze?, Mike Frysinger
• microblaze & nios, bjzhangwn
• edif to vhd black box, ccon67
  • Re: edif to vhd black box, Jim Wu
• Synplicity and the EDK, motty
  • Re: Synplicity and the EDK, Antti Lukats
• Going insane - Xilinx VGA controller..., peter.halford@xxxxxxxxxxx
  • Re: Going insane - Xilinx VGA controller..., Ed McGettigan
  • Re: Going insane - Xilinx VGA controller..., Dave
    • Re: Going insane - Xilinx VGA controller..., peter.halford@xxxxxxxxxxx
      • Re: Going insane - Xilinx VGA controller..., dp
  • Re: Going insane - Xilinx VGA controller..., Jim Granville
  • Re: Going insane - Xilinx VGA controller..., Sylvain Munaut
  • Re: Going insane - Xilinx VGA controller..., bh
  • Re: Going insane - Xilinx VGA controller..., peter.halford@xxxxxxxxxxx
    • Re: Going insane - Xilinx VGA controller..., Phil Hays
      • Re: Going insane - Xilinx VGA controller..., peter.halford@xxxxxxxxxxx
      • Re: Going insane - Xilinx VGA controller..., Symon
      • Re: Going insane - Xilinx VGA controller..., peter.halford@xxxxxxxxxxx
    • Re: Going insane - Xilinx VGA controller..., Jon Elson
• Cordic v2.0 : cordic translate algorithm problem, Tobias
• Opencores Can Controller, Marco
  • Re: Opencores Can Controller, Antti Lukats
  • Re: Opencores Can Controller, Tom
• Xilinbx Online store XC2C32A, XC2C64A missing ?, Jim Granville
  • Re: Xilinbx Online store XC2C32A, XC2C64A missing ?, Antti Lukats
  • Re: Xilinbx Online store XC2C32A, XC2C64A missing ?, Hal Murray
• Re: Cypress FX2 bandwidth problem, bp
  • Re: Cypress FX2 bandwidth problem, Antti Lukats
    • Re: Cypress FX2 bandwidth problem, damir
      • Re: Cypress FX2 bandwidth problem, Antti Lukats
      • Re: Cypress FX2 bandwidth problem, damir
• call for paper,expresscard specification, bjzhangwn
• lpc922, Anshat
  • Re: lpc922, Eric Smith
    • Re: lpc922, Ray Andraka
      • Re: lpc922, Eric Smith
• Buffers/Line drivers for 6pin JTAG?, Telenochek
  • Re: Buffers/Line drivers for 6pin JTAG?, John Adair
    • Re: Buffers/Line drivers for 6pin JTAG?, Telenochek
• Spartan 3 Digilent Board Expansion Connectors, Renniks
  • Re: Spartan 3 Digilent Board Expansion Connectors, Antti Lukats
• 8 in clock mux, Morten Leikvoll
• Can anyone have the evaluation board from xilinx and altera?, bjzhangwn
  • Re: Can anyone have the evaluation board from xilinx and altera?, Andy Peters
• FPGA DDR controller - CKE signal... do I need a pull down?, I. Ulises Hernandez
  • Re: FPGA DDR controller - CKE signal... do I need a pull down?, wtxwtx
• Is there anyboay work on the subject with the embeded system in the fpga?, bjzhangwn
  • Re: Is there anyboay work on the subject with the embeded system in the fpga?, Antti Lukats
    • Re: Is there anyboay work on the subject with the embeded system in the fpga?, bjzhangwn
      • Re: Is there anyboay work on the subject with the embeded system in the fpga?, Antti Lukats
      • Re: Is there anyboay work on the subject with the embeded system in the fpga?, bjzhangwn
      • Re: Is there anyboay work on the subject with the embeded system in the fpga?, Antti Lukats
    • Re: Is there anyboay work on the subject with the embeded system in the fpga?, Jeremy Stringer
      • Re: Is there anyboay work on the subject with the embeded system in the fpga?, Antti Lukats
• HOW IS GREY BOX VERIFICATION DONE, AAA
• exception (0xe06d7363) when creating a MicroBlaze from the ISE environment, Raymond
• Interactive Logic, Andrew Ward
• Xilinix Modular Flow, superman321
  • Re: Xilinix Modular Flow, Alan
  • Re: Xilinix Modular Flow, superman321
• Place and Route Algorithms, marco
  • Re: Place and Route Algorithms, Peter Alfke
    • Re: Place and Route Algorithms, Stephane
    • Re: Place and Route Algorithms, Kolja Sulimma
      • Re: Place and Route Algorithms, marco
      • Re: Place and Route Algorithms, Peter Alfke
      • Re: Place and Route Algorithms, Kolja Sulimma
    • Re: Place and Route Algorithms, Jim Granville
      • Re: Place and Route Algorithms: where's the fat?, Austin Lesea
      • Re: Place and Route Algorithms: where's the fat?, dp
      • Re: Place and Route Algorithms: where's the fat?, Andy Peters
      • Re: Place and Route Algorithms: where's the fat?, dp
      • Re: Place and Route Algorithms: where's the fat?, John_H
      • Re: Place and Route Algorithms: where's the fat?, Phil Hays
      • Re: Place and Route Algorithms: where's the fat?, John_H
      • Re: Place and Route Algorithms: where's the fat?, Jeremy Stringer
      • Re: Place and Route Algorithms: where's the fat?, Marc Randolph
      • Re: Place and Route Algorithms: where's the fat?, Ray Andraka
      • Re: Place and Route Algorithms: where's the fat?, Jim Granville
      • Re: Place and Route Algorithms: where's the fat?, Austin Lesea
      • Re: Place and Route Algorithms: where's the fat?, Jim Granville
      • Re: Place and Route Algorithms: where's the fat?, Ray Andraka
      • Re: Place and Route Algorithms: where's the fat?, Jim Granville
      • Re: Place and Route Algorithms: where's the fat?, Austin Lesea
      • Re: Place and Route Algorithms: where's the fat?, Ray Andraka
      • Re: Place and Route Algorithms: where's the fat? here's some beef?, Austin Lesea
      • Re: Place and Route Algorithms: where's the fat?, Andy Peters
  • Re: Place and Route Algorithms, Mike Treseler
  • Re: Place and Route Algorithms, Piotr Wyderski
• Re: real-time compression algorithms on fpga, Newman
• ISE project with a Microblaze submodule: timing constrains warning, Raymond
  • Re: ISE project with a Microblaze submodule: timing constrains warning, Steve
• Re: FPGA board checking, rmanand
• help: how to use ICAP of Virtex-II ?, lioupayphone
  • Re: help: how to use ICAP of Virtex-II ?, GaLaKtIkUs?
• software application on the virtex-ii pro, Eric
  • Re: software application on the virtex-ii pro, clemens fischer
  • Re: software application on the virtex-ii pro, Peter Ryser
    • Message not available
      • Re: software application on the virtex-ii pro, Peter Ryser
• Patents and (possible) Plagiarism, Anyone ever been in a similar situation?, JustJohn
  • Re: Patents and (possible) Plagiarism, Anyone ever been in a similar situation?, mr_reznat
    • Re: Patents and (possible) Plagiarism, Anyone ever been in a similar situation?, wtxwtx
      • Re: Patents and (possible) Plagiarism, Anyone ever been in a similar situation?, mr_reznat
      • Re: Patents and (possible) Plagiarism, Anyone ever been in a similar situation?, wtxwtx
  • Re: Patents and (possible) Plagiarism, Anyone ever been in a similar situation?, johnp
    • Re: Patents and (possible) Plagiarism, an open apology, JustJohn
    • Re: Patents and (possible) Plagiarism, Anyone ever been in a similar situation?, mr_reznat
      • Re: Patents and (possible) Plagiarism, Anyone ever been in a similar situation?, wtxwtx
      • Re: Patents and (possible) Plagiarism, Anyone ever been in a similar situation?, Peter Alfke
      • Re: Patents and (possible) Plagiarism, Anyone ever been in a similar situation?, wtxwtx
      • Re: Patents and (possible) Plagiarism, Anyone ever been in a similar situation?, Tim Wescott
      • Re: Patents and (possible) Plagiarism, Anyone ever been in a similar situation?, wtxwtx
      • Re: Patents and (possible) Plagiarism, Anyone ever been in a similar situation?, Peter Alfke
      • Re: Patents and (possible) Plagiarism, Anyone ever been in a similar situation?, mr_reznat
      • Re: Patents and (possible) Plagiarism, Anyone ever been in a similar situation?, wtxwtx
  • Re: Patents and (possible) Plagiarism, Anyone ever been in a similar situation?, John_H
    • Re: Patents and (possible) Plagiarism, Anyone ever been in a similar situation?, Pete Fraser
  • Re: Patents and (possible) Plagiarism, Anyone ever been in a similar situation?, Mike Treseler
    • Re: Patents and (possible) Plagiarism, Anyone ever been in a similar situation?, Ray Andraka
      • Re: Patents and (possible) Plagiarism, Anyone ever been in a similar situation?, langwadt
  • Re: Patents and (possible) Plagiarism, Anyone ever been in a similar situation?, Jon Elson
    • Re: Patents and (possible) Plagiarism, Anyone ever been in a similarsituation?, Jim Granville
      • Re: Patents and (possible) Plagiarism, Anyone ever been in a similarsituation?, Jon Elson
    • Re: Patents and (possible) Plagiarism, Anyone ever been in a similar situation?, soar2morrow
  • Re: Patents and (possible) Plagiarism, Anyone ever been in a similar situation?, wtxwtx
  • Re: Patents and (possible) Plagiarism, Anyone ever been in a similar situation?, wtxwtx
  • Re: Patents and (possible) Plagiarism, Anyone ever been in a similar situation?, Kolja Sulimma
• Mixing XC9500 and XC9500XL, also small qty suppliers, Philip Pemberton
  • Re: Mixing XC9500 and XC9500XL, also small qty suppliers, M.Randelzhofer
    • Re: Mixing XC9500 and XC9500XL, also small qty suppliers, Philip Pemberton
      • Re: Mixing XC9500 and XC9500XL, also small qty suppliers, Mika Leinonen
      • Re: Mixing XC9500 and XC9500XL, also small qty suppliers, Philip Pemberton
      • Re: Mixing XC9500 and XC9500XL, also small qty suppliers, M.Randelzhofer
  • Re: Mixing XC9500 and XC9500XL, also small qty suppliers, John Adair
    • Re: Mixing XC9500 and XC9500XL, also small qty suppliers, Philip Pemberton
• Virtex-4 Startup, GaLaKtIkUs?
  • Re: Virtex-4 Startup, Peter Ryser
  • Re: Virtex-4 Startup, Vic Vadi
    • Re: Virtex-4 Startup, GaLaKtIkUs?
• Virtex II Pro XC2VP100, rmanand
  • Re: Virtex II Pro XC2VP100, Nitro
    • Re: Virtex II Pro XC2VP100, rmanand
      • Re: Virtex II Pro XC2VP100, Antti Lukats
      • Re: Virtex II Pro XC2VP100, Duane Clark
      • Re: Virtex II Pro XC2VP100, rmanand
      • Re: Virtex II Pro XC2VP100, rmanand
• Re: ERROR:Pack:1564: ML403 & Xilinx Platform Studio 7.1.02i, kelau
  • Re: ERROR:Pack:1564: ML403 & Xilinx Platform Studio 7.1.02i, Newman
• Differential Pin Pairs in Lattice EC FPGAs, ALuPin@xxxxxx
  • Re: Differential Pin Pairs in Lattice EC FPGAs, Antti Lukats
    • Re: Differential Pin Pairs in Lattice EC FPGAs, ALuPin@xxxxxx
      • Re: Differential Pin Pairs in Lattice EC FPGAs, Antti Lukats
      • Re: Differential Pin Pairs in Lattice EC FPGAs, ALuPin@xxxxxx
• Problem with downloading elf file to ML403 using XMD, Thomas
  • Re: Problem with downloading elf file to ML403 using XMD, Florian
• where can i get a release copy of ISE 8i?, lioupayphone
  • Re: where can i get a release copy of ISE 8i?, Jon Beniston
  • Re: where can i get a release copy of ISE 8i?, Eli Hughes
• Powering unused MGTs in XC4VFX20CES2, Peter Rauschert
  • Re: Powering unused MGTs in XC4VFX20CES2, Peter Rauschert
    • Re: Powering unused MGTs in XC4VFX20CES2, Ed McGettigan
  • Re: Powering unused MGTs in XC4VFX20CES2, Austin Lesea
  • Re: Powering unused MGTs in XC4VFX20CES2, Ed McGettigan
• Re: Get Start for XtremeDSP Developement Board -IV, Scott Bekker
• How to use ISE FPGA Editor to compare timing path easily?, linq936
  • Re: How to use ISE FPGA Editor to compare timing path easily?, Duane Clark
• rs232 and picoblaze :), xavier.tastet@xxxxxxxxx
  • Re: rs232 and picoblaze :), Adrian Knoth
  • Re: rs232 and picoblaze :), Antti Lukats
• Altera based Video development board, Markus Knauss
  • Re: Altera based Video development board, Karl
    • Re: Altera based Video development board, Markus Knauss
      • Re: Altera based Video development board, Jan Panteltje
      • Re: Altera based Video development board, SDL
      • Re: Altera based Video development board, SDL
• know the Xilinx line? I need a good FAE or TSE in Austin, Texas, gdog
• Looking for QuickLogic DeskFab programmer, new or used, turbo . satan
• FPGA Implementation Of Real Time Data Compression, apurvewarrior@xxxxxxxxx
• How to simulate Virtex-4 PPC, MAC, etc. ?, acetylcholinerd@xxxxxxxxx
  • Re: How to simulate Virtex-4 PPC, MAC, etc. ?, Antti Lukats
• ISE 8.1i on Fedora Core 4 (64-bit), Eric Smith
  • Re: ISE 8.1i on Fedora Core 4 (64-bit), GaLaKtIkUs?
    • Re: ISE 8.1i on Fedora Core 4 (64-bit), Eric Smith
      • Re: ISE 8.1i on Fedora Core 4 (64-bit), Antti Lukats
• Interfacing externally clocked data to an FPGA (Spartan 3), Bart
  • Re: Interfacing externally clocked data to an FPGA (Spartan 3), Antti Lukats
    • Re: Interfacing externally clocked data to an FPGA (Spartan 3), johnp
      • Re: Interfacing externally clocked data to an FPGA (Spartan 3), Kolja Sulimma
      • Re: Interfacing externally clocked data to an FPGA (Spartan 3), Bart
      • Re: Interfacing externally clocked data to an FPGA (Spartan 3), johnp
      • Re: Interfacing externally clocked data to an FPGA (Spartan 3), wtxwtx
• Avnet hav2 s3e starter kit?, Alex Gibson
  • Re: Avnet hav2 s3e starter kit?, Antti Lukats
    • Re: Avnet hav2 s3e starter kit?, Antti Lukats
    • Re: Avnet hav2 s3e starter kit?, Steve Knapp (Xilinx Spartan-3 Generation FPGAs)
  • Re: Avnet hav2 s3e starter kit?, John_H
    • Re: Avnet hav2 s3e starter kit?, Antti Lukats
      • Re: Avnet hav2 s3e starter kit?, Steve Knapp (Xilinx Spartan-3 Generation FPGAs)
      • Re: Avnet hav2 s3e starter kit?, Antti Lukats
      • Re: Avnet hav2 s3e starter kit?, Steve Knapp (Xilinx Spartan-3 Generation FPGAs)
      • Re: Avnet hav2 s3e starter kit?, Glenn Jones
    • Re: Avnet hav2 s3e starter kit?, Brian Davis
    • Re: Avnet hav2 s3e starter kit?, Steve Knapp (Xilinx Spartan-3 Generation FPGAs)
  • Re: Avnet hav2 s3e starter kit?, Steve Knapp (Xilinx Spartan-3 Generation FPGAs)
    • Re: Avnet hav2 s3e starter kit?, Antti Lukats
    • Re: Avnet hav2 s3e starter kit?, jaxato
    • Re: Avnet hav2 s3e starter kit?, John_H
      • Re: Avnet hav2 s3e starter kit?, Antti Lukats
      • Re: Avnet hav2 s3e starter kit?, Alex Gibson
• Scrambled Net Names!, simon.stockton@xxxxxxxxxxxxxx
  • Re: Scrambled Net Names!, Symon
• Xilinx DCM Shuts down at 75degree centigrade, debashish . hota
  • Re: Xilinx DCM Shuts down at 75degree centigrade, PeteS
    • Re: Xilinx DCM Shuts down at 75degree centigrade, Peter Alfke
      • Re: Xilinx DCM Shuts down at 75degree centigrade, PeteS
  • Re: Xilinx DCM Shuts down at 75degree centigrade, Austin Lesea
    • Re: Xilinx DCM Shuts down at 75degree centigrade, Symon
• Parallel Cable III is not detected, singhal . prateek
  • Re: Parallel Cable III is not detected, erikdm
    • Re: Parallel Cable III is not detected, Prateek Singhal
      • Re: Parallel Cable III is not detected, nshrestha
  • Re: Parallel Cable III is not detected, erikdm
  • Re: Parallel Cable III is not detected, Jerzy Gbur
    • Re: Parallel Cable III is not detected, Prateek Singhal
• Digilent SRAM Controller, al99999
  • Re: Digilent SRAM Controller, Antti Lukats
    • Re: Digilent SRAM Controller, al99999
      • Re: Digilent SRAM Controller, Antti Lukats
      • Re: Digilent SRAM Controller, Leon
      • Re: Digilent SRAM Controller, al99999
      • Re: Digilent SRAM Controller, Brian Davis
• How to simulate a .NMC macro?, john
  • Re: How to simulate a .NMC macro?, Antti Lukats
    • Re: How to simulate a .NMC macro?, john
      • Re: How to simulate a .NMC macro?, Antti Lukats
• D FLIP -FLOP, AAA
  • Re: D FLIP -FLOP, AAA
  • Re: D FLIP -FLOP, DerekSimmons@xxxxxxxxxxxxxxx
• consensus theorem and power, fpgabuilder
  • Re: consensus theorem and power, JustJohn
    • Re: consensus theorem and power, fpgabuilder
      • Re: consensus theorem and power, Peter Alfke
• Xst Error, Ramakrishnan
  • Re: Xst Error, Paul Hartke
• Error in MAP (Xlinx Project navigator), Shantha
• Custom data rates with Virtex 2 Pro-X MGTs, jeffcannon
• Incremental Compilation in Quartus 5.1?, jjlindula@xxxxxxxxxxx
  • Re: Incremental Compilation in Quartus 5.1?, Banetele news
• FPGA-pci communication, Nitesh
  • Re: FPGA-pci communication, John Adair
    • Re: FPGA-pci communication, Nitesh
      • Re: FPGA-pci communication, Jerome
      • Re: FPGA-pci communication, Nitesh
      • Re: FPGA-pci communication, Jerome
      • Re: FPGA-pci communication, Nitesh
      • Re: FPGA-pci communication, john . orlando
      • Re: FPGA-pci communication, Nitesh
• Mission critical & low core voltages, Daveb
  • Re: Mission critical & low core voltages, Peter Alfke
    • Re: Mission critical & low core voltages, Daveb
      • Re: Mission critical & low core voltages, Peter Alfke
      • Re: Mission critical & low core voltages, Daveb
      • Re: Mission critical & low core voltages, Aurelian Lazarut
    • Re: Mission critical & low core voltages, David Belohrad
      • Re: Mission critical & low core voltages, Austin Lesea
  • Re: Mission critical & low core voltages, Austin Lesea
• Can ISE 4.2 program Virtex 2 6000K devices?, Frank
  • Re: Can ISE 4.2 program Virtex 2 6000K devices?, Gabor
    • Re: Can ISE 4.2 program Virtex 2 6000K devices?, Frank
• J Tag Protocol, ABS
  • Re: J Tag Protocol, Antti Lukats
    • Re: J Tag Protocol, PeteS
      • Re: J Tag Protocol, Neil Glenn Jacobson
    • Re: J Tag Protocol, ABS
      • Re: J Tag Protocol, Antti Lukats
• ISE WebPack 8.1i, GaLaKtIkUs?
  • Re: ISE WebPack 8.1i, backhus
    • Re: ISE WebPack 8.1i, GaLaKtIkUs?
      • Re: ISE WebPack 8.1i, Antti Lukats
      • Re: ISE WebPack 8.1i, Eric Smith
      • Re: ISE WebPack 8.1i, Antti Lukats
      • Re: ISE WebPack 8.1i, abgoyal
      • Re: ISE WebPack 8.1i, Stephane
• SGMII Interface, Jeremy Stringer
  • Re: SGMII Interface, PeteS
    • Re: SGMII Interface, Jeremy Stringer
• Frequency dependent SOPC builder components, avishay
  • Re: Frequency dependent SOPC builder components, Mark McDougall
    • Re: Frequency dependent SOPC builder components, avishay
      • Re: Frequency dependent SOPC builder components, Mark McDougall
• fiddling directly with LUT bits on Xilinx, John
  • Re: fiddling directly with LUT bits on Xilinx, John Adair
  • Re: fiddling directly with LUT bits on Xilinx, Antti Lukats
    • Re: fiddling directly with LUT bits on Xilinx, John_H
• Question about Progamming File generation report, GaLaKtIkUs?
  • Re: Question about Progamming File generation report, Gabor
    • Re: Question about Progamming File generation report, GaLaKtIkUs?
• Xilinx floating point core 1.0, kl31n
  • Re: Xilinx floating point core 1.0, mk
    • Re: Xilinx floating point core 1.0, kl31n
      • Re: Xilinx floating point core 1.0, rhnlogic
  • Re: Xilinx floating point core 1.0, Mike Treseler
    • Re: Xilinx floating point core 1.0, kl31n
      • Re: Xilinx floating point core 1.0, Robin Bruce
      • Re: Xilinx floating point core 1.0, Mike Treseler
  • Re: Xilinx floating point core 1.0, Ben Jones
• xilinx constraint, Monica
  • Re: xilinx constraint, amyler
    • Re: xilinx constraint, Monica
      • Re: xilinx constraint, amyler
      • Re: xilinx constraint, amyler
      • Re: xilinx constraint, Monica
      • Re: xilinx constraint, amyler
      • Re: xilinx constraint, Ray Andraka
      • Re: xilinx constraint, Jon Elson
      • Re: xilinx constraint, Monica
• mixed signal flash FPGAs launched!, Antti Lukats
  • Re: mixed signal flash FPGAs launched!, Jim Granville
    • Re: mixed signal flash FPGAs launched!, Antti Lukats
    • Re: mixed signal flash FPGAs launched!, Jan Panteltje
  • Re: mixed signal flash FPGAs launched!, Jan Panteltje
• Which decides my design's max frequency?, Binary
  • Re: Which decides my design's max frequency?, Mike Treseler
• Xilinx for PDP, hwguy
  • Re: Xilinx for PDP, Ray Andraka
• Xilinx FPGA - Wrongly Translated Inputs, Chloe
  • Re: Xilinx FPGA - Wrongly Translated Inputs, Zara
    • Re: Xilinx FPGA - Wrongly Translated Inputs, Chloe
      • Re: Xilinx FPGA - Wrongly Translated Inputs, Zara
• 3/2 with virtex 300, HB
  • Re: 3/2 with virtex 300, Symon
    • Re: 3/2 with virtex 300, Gabor
  • Re: 3/2 with virtex 300, Austin Lesea
    • Re: 3/2 with virtex 300, Symon
      • Re: 3/2 with virtex 300, Austin Lesea
      • Re: 3/2 with virtex 300, HB
      • Re: 3/2 with virtex 300, Symon
      • Re: 3/2 with virtex 300, Ray Andraka
      • Re: 3/2 with virtex 300, HB
      • Re: 3/2 with virtex 300, Ray Andraka
      • Re: 3/2 with virtex 300, Symon
• FPGA in industrial environment, calaf
  • Re: FPGA in industrial environment, Slurp
  • Re: FPGA in industrial environment, amyler
  • Re: FPGA in industrial environment, Austin Lesea
  • Re: FPGA in industrial environment, Balogh Viktor
• FreeRTOS.org has support for Microblaze, Richard
• modelsim settings in edk, Christoph Lauer
  • Re: modelsim settings in edk, Christoph Lauer
    • Re: modelsim settings in edk, GaLaKtIkUs?
• Question about Xilinx UCF files, GaLaKtIkUs?
  • Re: Question about Xilinx UCF files, Antti Lukats
    • Re: Question about Xilinx UCF files, GaLaKtIkUs?
• Re: Hello PPl, is there a way of locking a design (NGC) to a particular FPGA board?, Thomas Stanka
  • Re: Hello PPl, is there a way of locking a design (NGC) to a particular FPGA board?, Austin Lesea
    • Re: Hello PPl, is there a way of locking a design (NGC) to a particular FPGA board?, jaxato
      • Re: Hello PPl, is there a way of locking a design (NGC) to a particular FPGA board?, I. Ulises Hernandez
      • Re: Hello PPl, is there a way of locking a design (NGC) to a particular FPGA board?, Antti Lukats
      • Re: Hello PPl, is there a way of locking a design (NGC) to a particular FPGA board?, Ray Andraka
      • Re: Hello PPl, is there a way of locking a design (NGC) to a particular FPGA board?, Antti Lukats
      • Re: Hello PPl, is there a way of locking a design (NGC) to a particular FPGA board?, Ray Andraka
      • Re: Hello PPl, is there a way of locking a design (NGC) to a particular FPGA board?, JustJohn
      • Re: Hello PPl, is there a way of locking a design (NGC) to a particular FPGA board?, Ray Andraka
      • Re: Hello PPl, is there a way of locking a design (NGC) to a particular FPGA board?, Antti Lukats
      • Re: Hello PPl, is there a way of locking a design (NGC) to a particular FPGA board?, Ray Andraka
      • Re: Hello PPl, is there a way of locking a design (NGC) to a particular FPGA board?, Antti Lukats
      • Re: Hello PPl, is there a way of locking a design (NGC) to a particular FPGA board?, jaxato
      • Re: Hello PPl, is there a way of locking a design (NGC) to a particular FPGA board?, Ray Andraka
      • Re: Hello PPl, is there a way of locking a design (NGC) to a particular FPGA board?, Symon
      • Re: Hello PPl, is there a way of locking a design (NGC) to a particular FPGA board?, Hal Murray
      • Re: Hello PPl, is there a way of locking a design (NGC) to a particular FPGA board?, I. Ulises Hernandez
    • Re: Hello PPl, is there a way of locking a design (NGC) to a particular FPGA board?, henk
      • Re: Hello PPl, is there a way of locking a design (NGC) to a particular FPGA board?, jaxato
  • <Possible follow-ups>
  • Re: Hello PPl, is there a way of locking a design (NGC) to a particular FPGA board?, Jim Granville
    • Re: Hello PPl, is there a way of locking a design (NGC) to a particular FPGA board?, Symon
      • Re: Hello PPl, is there a way of locking a design (NGC) to a particular FPGA board?, David Brown
  • Re: Hello PPl, is there a way of locking a design (NGC) to a particular FPGA board?, JustJohn
    • Re: Hello PPl, is there a way of locking a design (NGC) to a particular FPGA board?, Antti Lukats
• who can help me? i want to know the bitsream format of Virtex-II, lioupayphone
  • Re: who can help me? i want to know the bitsream format of Virtex-II, Frank
    • Re: who can help me? i want to know the bitsream format of Virtex-II, GaLaKtIkUs?
      • Re: who can help me? i want to know the bitsream format of Virtex-II, Frank
      • Re: who can help me? i want to know the bitsream format of Virtex-II, Javier Castillo
      • Re: who can help me? i want to know the bitsream format of Virtex-II, Ray Andraka
      • Re: who can help me? i want to know the bitsream format of Virtex-II, Symon
      • Re: who can help me? i want to know the bitsream format of Virtex-II, Ray Andraka
      • Re: who can help me? i want to know the bitsream format of Virtex-II, Antti Lukats
• When read back bitstreams from Xilinx PROMs, how to verify?, Frank
• About Spartan 3, Piotr Wyderski
  • Re: About Spartan 3, Antti Lukats
• MMC(MultiMedia Card) interfacing with FPGA, fahadislam2002
  • Re: MMC(MultiMedia Card) interfacing with FPGA, Antti Lukats
    • Re: MMC(MultiMedia Card) interfacing with FPGA, Kryten
      • Re: MMC(MultiMedia Card) interfacing with FPGA, Antti Lukats
      • Re: MMC(MultiMedia Card) interfacing with FPGA, Kryten
      • Re: MMC(MultiMedia Card) interfacing with FPGA, Martin Schoeberl
      • Re: MMC(MultiMedia Card) interfacing with FPGA, Antti Lukats
      • Re: MMC(MultiMedia Card) interfacing with FPGA, Martin Schoeberl
      • Re: MMC(MultiMedia Card) interfacing with FPGA, Antti Lukats
  • re:MMC(MultiMedia Card) interfacing with FPGA, fahadislam2002
    • Re: re:MMC(MultiMedia Card) interfacing with FPGA, Antti Lukats
  • re:MMC(MultiMedia Card) interfacing with FPGA, fahadislam2002
• Problem with ChipScope Pro 6.2, Sudhir . Singh
  • Re: Problem with ChipScope Pro 6.2, Antti Lukats
  • Re: Problem with ChipScope Pro 6.2, svasus
  • Re: Problem with ChipScope Pro 6.2, Anup Raghavan
• First IP-core designed for and tested with Spartan-3E, Antti Lukats
  • Re: First IP-core designed for and tested with Spartan-3E, Alan Nishioka
    • Re: First IP-core designed for and tested with Spartan-3E, Antti Lukats
      • Re: First IP-core designed for and tested with Spartan-3E, Alan Nishioka
• Xilinx ML40x VGA Documentation, Brad Smallridge
  • Re: Xilinx ML40x VGA Documentation, Antti Lukats
• Securing verilog source code, fad
  • Re: Securing verilog source code, Hans
    • Re: Securing verilog source code, fad
• Adding "super-LUTs" to FPGA, good idea ?, Sylvain Munaut
  • Re: Adding "super-LUTs" to FPGA, good idea ?, Antti Lukats
    • Re: Adding "super-LUTs" to FPGA, good idea ?, Sylvain Munaut
      • Re: Adding "super-LUTs" to FPGA, good idea ?, Antti Lukats
    • Re: Adding "super-LUTs" to FPGA, good idea ?, Ray Andraka
      • Re: Adding "super-LUTs" to FPGA, good idea ?, Sylvain Munaut
      • Re: Adding "super-LUTs" to FPGA, good idea ?, Ray Andraka
      • Re: Adding "super-LUTs" to FPGA, good idea ?, juendme
      • Re: Adding "super-LUTs" to FPGA, good idea ?, Morten Leikvoll
  • Re: Adding "super-LUTs" to FPGA, good idea ?, Kolja Sulimma
    • Re: Adding "super-LUTs" to FPGA, good idea ?, Peter Alfke
      • Important BRAM safety tip ( was: Adding "super-LUTs" to FPGA, good idea ?), Brian Davis
      • Re: Important BRAM safety tip ( was: Adding "super-LUTs" to FPGA, good idea ?), Peter Alfke
      • Re: Important BRAM safety tip ( was: Adding "super-LUTs" to FPGA, good idea ?), Brian Davis
      • Re: Important BRAM safety tip ( was: Adding "super-LUTs" to FPGA, good idea ?), Jim Granville
      • Re: Important BRAM safety tip ( was: Adding "super-LUTs" to FPGA, good idea ?), Brian Davis
      • Re: Important BRAM safety tip ( was: Adding "super-LUTs" to FPGA, good idea ?), Bob Perlman
      • Re: Important BRAM safety tip ( was: Adding "super-LUTs" to FPGA, good idea ?), Ray Andraka
      • Re: Important BRAM safety tip ( was: Adding "super-LUTs" to FPGA, good idea ?), John_H
• XC4VFX12 -- availability?, acetylcholinerd@xxxxxxxxx
  • Re: XC4VFX12 -- availability?, Antti Lukats
    • Re: XC4VFX12 -- availability?, Austin Lesea
      • Re: XC4VFX12 -- availability?, Antti Lukats
      • Re: XC4VFX12 -- availability?, Finn S. Nielsen
      • Re: XC4VFX12 -- availability?, Peter Alfke
• ISE purchase, Roger
  • Re: ISE purchase, Antti Lukats
    • Re: ISE purchase, Eric Smith
      • Re: ISE purchase, Roger
      • Re: ISE purchase, Eric Smith
      • Re: ISE purchase, john . orlando
      • Re: ISE purchase, Eric Smith
  • Re: ISE purchase, John Adair
  • Re: ISE purchase, Brian Drummond
  • Re: ISE purchase, Stephen Craven
    • Re: ISE purchase, John Adair
• No, not FIFOs again..., Thomas Entner
  • Re: No, not FIFOs again..., Peter Alfke
    • Re: No, not FIFOs again..., Thomas Entner
      • Re: No, not FIFOs again..., Antti Lukats
      • Re: No, not FIFOs again..., Thomas Entner
      • Re: No, not FIFOs again..., John_H
      • Re: No, not FIFOs again..., Thomas Entner
      • Re: No, not FIFOs again..., Peter Alfke
      • Re: No, not FIFOs again..., Thomas Entner
      • Re: No, not FIFOs again..., Ray Andraka
      • Re: No, not FIFOs again..., Peter Alfke
• ISE = Intelligent Synthesis Expectable :-), backhus
  • Re: ISE = Intelligent Synthesis Expectable :-), Jan Decaluwe
    • Re: ISE = Intelligent Synthesis Expectable :-), backhus
      • Re: ISE = Intelligent Synthesis Expectable :-), johnp
      • Re: ISE = Intelligent Synthesis Expectable :-), backhus
      • Re: ISE = Intelligent Synthesis Expectable :-), Jan Decaluwe
      • Re: ISE = Intelligent Synthesis Expectable :-), backhus
• How do I find the signature of PROM bitstreams?, Frank
  • Re: How do I find the signature of PROM bitstreams?, Aurelian Lazarut
• FPGA : MAP slice logic into BLOCK RAM, bijoy
  • Re: FPGA : MAP slice logic into BLOCK RAM, Antti Lukats
    • Re: FPGA : MAP slice logic into BLOCK RAM, bijoy
      • Re: FPGA : MAP slice logic into BLOCK RAM, wv9557
  • Re: FPGA : MAP slice logic into BLOCK RAM, bijoy
• Experiences with Actel ProAsic3E and toolchain?, jweissberg
  • Re: Experiences with Actel ProAsic3E and toolchain?, Antti Lukats
  • Re: Experiences with Actel ProAsic3E and toolchain?, vinogradov . slava
  • Re: Experiences with Actel ProAsic3E and toolchain?, Hans
• Replace fast ethernet with VDSL2, fpgakid@xxxxxxxxx
  • Re: Replace fast ethernet with VDSL2, Simon Peacock
  • Re: Replace fast ethernet with VDSL2, Dal
• [ISE7.1] Equivalent register removal + register duplication + register balancing, Tim Verstraete
• partial reconfig of Virtex-4 : iMPACT warning makes the chip pause, Denaice
  • Re: partial reconfig of Virtex-4 : iMPACT warning makes the chip pause, Javier Castillo
    • Re: partial reconfig of Virtex-4 : iMPACT warning makes the chip pause, Denaice
      • Re: partial reconfig of Virtex-4 : iMPACT warning makes the chip pause, Antti Lukats
      • Re: partial reconfig of Virtex-4 : iMPACT warning makes the chip pause, Javier Castillo
      • Re: partial reconfig of Virtex-4 : iMPACT warning makes the chip pause, Denaice
      • Re: partial reconfig of Virtex-4 : iMPACT warning makes the chip pause, Javier Castillo
• Post PAR Simulation and Actual FPGA results differ, Sudhir . Singh
  • Re: Post PAR Simulation and Actual FPGA results differ, ALuPin@xxxxxx
  • Re: Post PAR Simulation and Actual FPGA results differ, Jeff Cunningham
    • Re: Post PAR Simulation and Actual FPGA results differ, Sudhir . Singh
      • Re: Post PAR Simulation and Actual FPGA results differ, juendme
  • Re: Post PAR Simulation and Actual FPGA results differ, info_
• 2 clocks switching, rybol
  • Re: 2 clocks switching, Peter Alfke
  • Re: 2 clocks switching, Aurelian Lazarut
  • Re: 2 clocks switching, Len
  • Re: 2 clocks switching, Len
• Simulating Post-Synthesis Model on Xilinx FPGA, Chloe
  • Re: Simulating Post-Synthesis Model on Xilinx FPGA, ghelbig
    • Re: Simulating Post-Synthesis Model on Xilinx FPGA, Chloe
      • Re: Simulating Post-Synthesis Model on Xilinx FPGA, ghelbig
      • Re: Simulating Post-Synthesis Model on Xilinx FPGA, Chloe
      • Re: Simulating Post-Synthesis Model on Xilinx FPGA, Mike Treseler
      • Re: Simulating Post-Synthesis Model on Xilinx FPGA, Chloe
      • Re: Simulating Post-Synthesis Model on Xilinx FPGA, Ray Andraka
      • Re: Simulating Post-Synthesis Model on Xilinx FPGA, Newman
      • Re: Simulating Post-Synthesis Model on Xilinx FPGA, Chloe
  • Re: Simulating Post-Synthesis Model on Xilinx FPGA, Ray Andraka
  • <Possible follow-ups>
  • Simulating Post-Synthesis Model on Xilinx FPGA, Chloe
• Virtex 4 not meeting timing constraints, Scott Bekker
  • Re: Virtex 4 not meeting timing constraints, Jeff Cunningham
  • Re: Virtex 4 not meeting timing constraints, Ray Andraka
    • Re: Virtex 4 not meeting timing constraints, Scott Bekker
      • Re: Virtex 4 not meeting timing constraints, Ray Andraka
• some new PCIe products, Antti Lukats
  • Re: some new PCIe products, Ben Twijnstra
    • Re: some new PCIe products, Antti Lukats
      • Re: some new PCIe products, Jeff Cunningham
      • Re: some new PCIe products, Antti Lukats
• PLX 9056 application, Alex
  • Re: PLX 9056 application, Alan Nishioka
• Embedded ppc405 w/o RAM?, reidek
  • Re: Embedded ppc405 w/o RAM?, Antti Lukats
    • Re: Embedded ppc405 w/o RAM?, Kunal Shenoy
      • Re: Embedded ppc405 w/o RAM?, Peter Alfke
      • Re: Embedded ppc405 w/o RAM?, reidek@xxxxxxxxx
      • Re: Embedded ppc405 w/o RAM?, Austin Lesea
      • Re: Embedded ppc405 w/o RAM?, reidek@xxxxxxxxx
      • Re: Embedded ppc405 w/o RAM?, Austin Lesea
  • Re: Embedded ppc405 w/o RAM?, Peter Ryser
• Re: ML402 DDR SDRAM, Jihoon
  • <Possible follow-ups>
  • Re: ML402 DDR SDRAM, Jihoon
• A stupid question about constraints, GaLaKtIkUs?
  • Re: A stupid question about constraints, jerzy.gbur@xxxxxxxxx
    • Re: A stupid question about constraints, GaLaKtIkUs?
      • Re: A stupid question about constraints, Antti Lukats
• Re: Partial Reconfiguration Problems, Andreas Kühn
• Problem programming CoolRunner II xc2c256_tq144 CPLD using IMPACT, nshrestha
  • Re: Problem programming CoolRunner II xc2c256_tq144 CPLD using IMPACT, Aurelian Lazarut
  • Re: Problem programming CoolRunner II xc2c256_tq144 CPLD using IMPACT, Antti Lukats
• Free x86 IP-Core is really working!, Antti Lukats
  • Re: Free x86 IP-Core is really working!, Hans
    • Re: Free x86 IP-Core is really working!, Antti Lukats
    • Re: Free x86 IP-Core is really working!, Antti Lukats
• Stratix EP1S80 DSP development board (Problem for ADC/DAC conversion ), ylc199
  • Re: Stratix EP1S80 DSP development board (Problem for ADC/DAC conversion ), Rene Tschaggelar
    • Re: Stratix EP1S80 DSP development board (Problem for ADC/DAC conversion ), ylc199
• FPGA development board with digital image camera, hongying meng
  • Re: FPGA development board with digital image camera, Antti Lukats
  • Re: FPGA development board with digital image camera, Michael
  • Re: FPGA development board with digital image camera, Gabor
    • Re: FPGA development board with digital image camera, Antti Lukats
      • Re: FPGA development board with digital image camera, Joseph Samson
      • Re: FPGA development board with digital image camera, Antti Lukats
      • Re: FPGA development board with digital image camera, Michael
  • Re: FPGA development board with digital image camera, Jan Panteltje
  • Re: FPGA development board with digital image camera, Paul Hartke
    • Re: FPGA development board with digital image camera, Antti Lukats
  • Re: FPGA development board with digital image camera, kempaj
• Free Seminars - UK, John Adair
• VERIFICATION AND TESTING, Abbs
  • Re: VERIFICATION AND TESTING, Thomas Stanka
    • Re: VERIFICATION AND TESTING, Abbs
      • Re: VERIFICATION AND TESTING, Hans
      • Re: VERIFICATION AND TESTING, Abbs
• I2C controller chipset to interface with FPGA, svasus
  • Re: I2C controller chipset to interface with FPGA, Antti Lukats
    • Re: I2C controller chipset to interface with FPGA, Martin Thompson
    • Re: I2C controller chipset to interface with FPGA, Eric Smith
      • Re: I2C controller chipset to interface with FPGA, Antti Lukats
      • Re: I2C controller chipset to interface with FPGA, Eric Smith
      • Re: I2C controller chipset to interface with FPGA, Jim Granville
  • Re: I2C controller chipset to interface with FPGA, Jim Granville
    • Re: I2C controller chipset to interface with FPGA, Jim Granville
  • Re: I2C controller chipset to interface with FPGA, Kryten
    • Re: I2C controller chipset to interface with FPGA, Jim Granville
      • Re: I2C controller chipset to interface with FPGA, Ray Andraka
  • Re: I2C controller chipset to interface with FPGA, Petter Gustad
  • Re: I2C controller chipset to interface with FPGA, Kolja Sulimma
• How to connect 2 FPGA?, Marco
  • Re: How to connect 2 FPGA?, Antti Lukats
    • Re: How to connect 2 FPGA?, Marco
      • Re: How to connect 2 FPGA?, Antti Lukats
      • Re: How to connect 2 FPGA?, Uwe Bonnes
      • Re: How to connect 2 FPGA?, Carsten
      • Re: How to connect 2 FPGA?, Marco
      • Re: How to connect 2 FPGA?, PeteS
  • Re: How to connect 2 FPGA?, Rene Tschaggelar
• fpga tutorial?, aiiadict
• Re: ISE SP4 installer on Linux, GaLaKtIkUs?
• [IGNORE] TEST, Lukasz Salwinski
• Job available... 2 projects, aiiadict
  • Re: Job available... 2 projects, bijoy
  • re:Job available... 2 projects, acidocinico
  • re:Job available... 2 projects, fahadislam2002
• XUP PLATFORM USB CHIPSCOPE COMPATIBILITY PROBLEMS, jaxato
  • Re: XUP PLATFORM USB CHIPSCOPE COMPATIBILITY PROBLEMS, Paul Hartke
    • Re: XUP PLATFORM USB CHIPSCOPE COMPATIBILITY PROBLEMS, jaxato
      • Re: XUP PLATFORM USB CHIPSCOPE COMPATIBILITY PROBLEMS, Paul Hartke
      • Re: XUP PLATFORM USB CHIPSCOPE COMPATIBILITY PROBLEMS, jaxato
      • Re: XUP PLATFORM USB CHIPSCOPE COMPATIBILITY PROBLEMS, Jan Tjernberg
• Re: xilinx research labs, porterboy76
  • Re: xilinx research labs, Steven Derrien
    • Re: xilinx research labs, jaxato
      • Re: xilinx research labs, Antti Lukats
  • Re: xilinx research labs, Austin Lesea
    • Re: xilinx research labs, Steven Derrien
      • Re: xilinx research labs, Austin Lesea
  • Re: xilinx research labs, Stephen
    • Re: xilinx research labs, Steven Derrien
      • Re: xilinx research labs, Stephen
      • Re: xilinx research labs, porterboy76
• VHDL SPI core, Marco
  • Re: VHDL SPI core, Andy Peters
    • Re: VHDL SPI core, rponsard
  • <Possible follow-ups>
  • VHDL SPI core, Marco
    • Re: VHDL SPI core, Mark McDougall
• IDE for Nios2 does not compile on windows XP, Michael
  • Re: IDE for Nios2 does not compile on windows XP, Thomas Entner
    • Re: IDE for Nios2 does not compile on windows XP, Michael
• Re: Clock problem? Altera Stratix-II ES and MP, gregs
  • Re: Clock problem? Altera Stratix-II ES and MP, Tomoya
• Re: Is it legal to write an logical equation for a FPGA LUT in claims of a patent?, Kolja Sulimma
  • <Possible follow-ups>
  • Re: Is it legal to write an logical equation for a FPGA LUT in claims of a patent?, John Williams
• Re: ISE 8.1 news--BaseX going away, but WebPack gains devices and features, Ryan Jones
• ISE 8.1 release delayed?, Antti Lukats
  • Re: ISE 8.1 release delayed?, Simon Peacock
    • Re: ISE 8.1 release delayed?, Ray Andraka
      • Re: ISE 8.1 release delayed?, Antti Lukats
  • Re: ISE 8.1 release delayed?, Andy Peters
    • Re: ISE 8.1 release delayed?, Symon
    • Re: ISE 8.1 release delayed?, Symon
    • Re: ISE 8.1 release delayed?, Jim Granville
      • Re: ISE 8.1 release delayed?, Antti Lukats
  • Re: ISE 8.1 release delayed?, Phil Hays
• Use EMC to control a FIFO ?, kenton
• Virtex-4 DSP48 placement restrictions?, Brian Drummond
  • Re: Virtex-4 DSP48 placement restrictions?, Brian Drummond
  • Re: Virtex-4 DSP48 placement restrictions?, Ray Andraka
    • Re: Virtex-4 DSP48 placement restrictions?, Brian Drummond
      • Re: Virtex-4 DSP48 placement restrictions?, Ray Andraka
• Chipscope under Linux, GaLaKtIkUs?
  • Re: Chipscope under Linux, GaLaKtIkUs?
• programming flash memeory, Lina
  • Re: programming flash memeory, Antti Lukats
  • Re: programming flash memeory, Lina
• Power Optimization NetSeminar: Wedesday, Dec. 7 at 11 am PST, Vaughn Betz
  • Re: Power Optimization NetSeminar: Wedesday, Dec. 7 at 11 am PST, Jim Granville
    • Re: Power Optimization NetSeminar: Wedesday, Dec. 7 at 11 am PST, Vaughn Betz
• Re: Black Box Attribute in Quartus II, Vaughn Betz
  • Re: Black Box Attribute in Quartus II, kedarpapte
  • Re: Black Box Attribute in Quartus II, Ken McElvain
• Tip: Spotlight (OS X) indexing of VHDL files, c d saunter
  • Re: Tip: Spotlight (OS X) indexing of VHDL files, Andy Peters
    • Re: Tip: Spotlight (OS X) indexing of VHDL files, Eli Hughes
      • Re: Tip: Spotlight (OS X) indexing of VHDL files, c d saunter
• how to build 32X32 LUT ROM, bachimanchi
  • Re: how to build 32X32 LUT ROM, John Retta
  • Re: how to build 32X32 LUT ROM, John Adair
  • Re: how to build 32X32 LUT ROM, Simon Peacock
• Problem Timing Simulation CoolRunner II Design Kit, nshrestha
• Looking for FPGA Programming consultant, nahum
• Using RiscWatch with Xilinx FPGA's for powerpc, Pankaj
  • Re: Using RiscWatch with Xilinx FPGA's for powerpc, Antti Lukats
• Hardware Modeling Verification, Akhil
• ML403 "small" problem, GaLaKtIkUs?
  • Re: ML403 "small" problem, Peter Ryser
  • Re: ML403 "small" problem, Erik Widding
    • Re: ML403 "small" problem, GaLaKtIkUs?
• internal clock, hirenshah.05@xxxxxxxxx
  • Re: internal clock, Antti Lukats
• problem with timing simulation (clear explanation of problem), bachimanchi
  • Re: problem with timing simulation (clear explanation of problem), Aurelian Lazarut
• Re: Pal programming requirement, aptecelectronics
  • Re: Pal programming requirement, Simon Peacock
• problem with timing simulation, bachimanchi
• Xilinx V4 ISERDES problem, Brad Smallridge
  • Re: Xilinx V4 ISERDES problem, joseph
    • Re: Xilinx V4 ISERDES problem, Brad Smallridge
• Synthesize: Error, Simon
  • Re: Synthesize: Error, Brad Smallridge
  • Re: Synthesize: Error, Andy Peters
    • Re: Synthesize: Error, Simon
      • Re: Synthesize: Error, mk
• Re: first time managing a project, Brendan Cullen
  • Re: first time managing a project, amyler
• Spartan3E availability update, Antti Lukats
  • Re: Spartan3E availability update, Raymund Hofmann
    • Re: Spartan3E availability update, Simon Peacock
      • Re: Spartan3E availability update, Antti Lukats
• Virtex 4 IDELAY implementation, kyeyk
  • Re: Virtex 4 IDELAY implementation, Jim Wu
  • re:Virtex 4 IDELAY implementation, kyeyk
• Xilinx FPGA - Behaviorial Model Transferred Instead of Place-and-routed Model, Chloe
  • Re: Xilinx FPGA - Behaviorial Model Transferred Instead of Place-and-routed Model, Ryan Jones
  • Re: Xilinx FPGA - Behaviorial Model Transferred Instead of Place-and-routed Model, John Adair
    • Re: Xilinx FPGA - Behaviorial Model Transferred Instead of Place-and-routed Model, Chloe
      • Re: Xilinx FPGA - Behaviorial Model Transferred Instead of Place-and-routed Model, Chloe
• FPGA : Decimation Filter Implementation, bijoy
  • Re: FPGA : Decimation Filter Implementation, Simon Peacock
    • Re: FPGA : Decimation Filter Implementation, Symon
      • Re: FPGA : Decimation Filter Implementation, Simon Peacock
      • Re: FPGA : Decimation Filter Implementation, Symon
      • Re: FPGA : Decimation Filter Implementation, Simon Peacock
      • Re: FPGA : Decimation Filter Implementation