Re: async fifo design
- From: "Peter Alfke" <alfke@xxxxxxxxxxxxx>
- Date: 29 Nov 2005 19:15:09 -0800
Michael,
FULL is a control signal for the writing (and EMPTYis a control signal
for the reading).
As I said, the leading edges are naturally derived from the appropriate
clock, and are thus synchronous.
The falling edges are caused by the "wrong" clock, and can thushave any
weird phase relationship with the important clock.
You do not want the FULL flag go away in an asynchronous way, since
that might "confuse" the write logic, whether it can or cannot write at
this moment.
And the trailing edge of EMPTY should clearly communicate with the read
logic, in an unambiguous way. These flags must be interpreted
correctly for many millions of times, any ambiguity will bite you,
sooner or later. Usually in the worst way (Murphy's Law).
Peter Alfke
.
- References:
- async fifo design
- From: Michael Dreschmann
- Re: async fifo design
- From: Charles, NG
- Re: async fifo design
- From: Michael Dreschmann
- Re: async fifo design
- From: C. G.
- Re: async fifo design
- From: Peter Alfke
- Re: async fifo design
- From: Michael Dreschmann
- async fifo design
- Prev by Date: Re: Q-bus or Unibus bus transactions in FPGA?
- Next by Date: Xilinx Coregen IP Customizer Causes Exception During Customization
- Previous by thread: Re: async fifo design
- Next by thread: Re: async fifo design
- Index(es):
Relevant Pages
|
