Re: Virtex 4 Tapped Delay Lines
- From: "Symon" <symon_brewer@xxxxxxxxxxx>
- Date: 29 Nov 2005 19:40:42 +0100
"Philip Freidin" <philip@xxxxxxxxxxxxxxx> wrote in message
news:ji6mo15amnurn107gkp4s0a4uof39pkrbp@xxxxxxxxxx
>
> I think it is best to distribute the signal on your PCB.
>
...but be aware of the load you're placing on the signal. The FPGA's pins
have considerable capacitance. If you wire the signal to 8 pins, you could
have 100pF loading the end of your line. This gives you a rise time of the
order of 5ns if driven from 50 ohms. The timing might be skewed as the
signal rises through the thresholds of the inputs.
Cheers, Syms.
p.s. I'm wondering if you could use some spare unbonded IOBs for this? Take
the signal in. Distribute it with low skew (easy to say!) to the outputs of
4 or 8 unbonded IOBs. Use the input delay thingies? The same as previously
suggested, but without using up real IOBs?
.
- References:
- Virtex 4 Tapped Delay Lines
- From: al99999
- re:Virtex 4 Tapped Delay Lines
- From: al99999
- Re: Virtex 4 Tapped Delay Lines
- From: Philip Freidin
- Virtex 4 Tapped Delay Lines
- Prev by Date: Re: boot from flah
- Next by Date: Re: Virtex 4 Tapped Delay Lines
- Previous by thread: Re: Virtex 4 Tapped Delay Lines
- Next by thread: Re: Virtex 4 Tapped Delay Lines
- Index(es):
