Re: Slow FIFO using external SRAM
- From: "Arlet" <usenet+5@xxxxxxxxxxxxxxxxx>
- Date: 29 Nov 2005 12:02:26 -0800
damir wrote:
> I need to implement slow FIFO (16-bit wide, max. 10 MHz) using external
> single-port SRAM connected to the FPGA (Spartan II/III).
>
> Does anyone have similar FIFO controller (sync/async) implemented using
> VHDL?
>
> Thanks,
>
> Damir
I would put two small FIFOs on the FPGA, and then have a simple,
synchronous state machine to control the external RAM. The state
machine would look at how full/empty the FIFOs are, and based on their
priority determine whether it will do a either a read or write access
to the external RAM.
If you need an asych FIFO, then use one of the on-chip FIFOs to cross
the clock domains, and keep the rest on the same clock.
.
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- Slow FIFO using external SRAM
- From: damir
- Slow FIFO using external SRAM
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