Re: Slow FIFO using external SRAM
- From: "damir" <dzagar@xxxxxxxxxxxx>
- Date: Tue, 29 Nov 2005 20:53:05 +0100
Thanks for the hint, I'll try this approach!
Damir
"Peter Alfke" <peter@xxxxxxxxxx> wrote in message
news:1133292476.312758.278240@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
>I would design a reasonably fast state machine ( 50 MHz?) that keeps
> track of the read and write requests, updates the two addresses and
> multiplexes them appropriately to the external SRAM. If read-access
> time is important, you could always pre-fetch the next entry and store
> it in an on-chip register. The state machine must check for the two
> addresses becoming equal. If read causes them to become equal, the FIFO
> is empty, if write causes it, the FIFO is full.
> The slow speed makes all this possible, and even easy.
> Don't worry too much about metastability of the control circuitry. Just
> make sure that there is an extra 5 ns of settling-time slack available.
> Peter Alfke, Xilinx Applications
>
.
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